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ADC08B3000 Datasheet (HTML) - National Semiconductor

Part No. ADC08B3000
Description  High Performance, Low Power, 8-Bit, 3 GSPS A/D Converter with 4K Buffer
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Maker  NSC [National Semiconductor]
Homepage  http://www.national.com
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Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
3
SCLK
Serial Interface Clock. When the extended control mode is
enabled, this pin functions as the SCLK input which clocks in
the serial data.See Section 1.2 for details on the extended
control mode. See Section 1.3 for description of the serial
interface. When not in extended control mode, tie to ground.
4
OutEdge / DDR
/ SDATA
Edge Select, Double Data Rate Enable and Serial Data Input.
This input sets the edge of DRDY at which the output data
transitions. (See Section 1.1.5.2). When this pin is floating or
connected to 1/2 the supply voltage, DDR clocking is
enabled. When the extended control mode is enabled, this pin
functions as the SDATA input. See Section 1.2 for details on
the extended control mode. See Section 1.3 for description of
the serial interface.
15
ADCCLK_RST
ADC Sample Clock Reset. A positive pulse on this pin is used
to reset and synchronize the ADC sampling clock.
26
PD
Power Down Pins. A logic high on the PD pin puts the entire
device into the Power Down Mode.
30
CAL
Calibration Cycle Initiate. A minimum 80 input clock cycles
logic low followed by a minimum of 80 input clock cycles high
on this pin initiates the self calibration sequence. See Section
2.4.2 for an overview of self-calibration and Section 2.4.2.2
for a description of on-command calibration.
14
FSR/ECE
Full Scale Range Select and Extended Control Enable. In
non-extended control mode, a logic low on this pin sets the
full-scale differential input range to 600 mV
P-P. A logic high on
this pin sets the full-scale differential input range to 800
mV
P-P. See Section 1.1.4. To enable the extended control
mode, whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage
equal to V
A/2. See Section 1.2 for information on the
extended control mode.
127
CalDly / SCS
Calibration Delay and Serial Interface Chip Select. With a
logic high or low on pin 14, this pin functions as Calibration
Delay and sets the number of input clock cycles after power
up before calibration begins (See Section 1.1.1). With pin 14
floating, this pin acts as the enable pin for the serial interface
input and the CalDly value becomes "0" (short delay with no
provision for a long power-up calibration delay).
10
11
CLK+
CLK-
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See Section 1.1.2 for a
description of acquiring the input and Section 2.3 for an
overview of the clock inputs.
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