ADC08B3000 datasheet(19/32 Pages) NSC

Part #	ADC08B3000

Description	High Performance, Low Power, 8-Bit, 3 GSPS A/D Converter with 4K Buffer

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Manufacturer	NSC [National Semiconductor (TI)]

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1.0 Functional Description (Continued)

Two full-scale range settings are provided with pin 14 (FSR).

A high on pin 14 causes an input full-scale range setting of

800 mV

P-P, while grounding pin 14 causes an input full-scale

range setting of 600 mV

P-P. The full-scale range setting

operates equally on both ADCs.

In the Extended Control mode, the full-scale input range can

be set to values between 560 mV

P-P and 840 mVP-P through

a serial interface. See Section 2.2

1.1.5 Clocking

The ADC08B3000 must be driven with an a.c. coupled,

differential clock signal. Section 2.3 describes the use of the

clock input pins. To assist the user in offloading captured

data from the Capture Buffer, the ADC08B3000 has an

RCLK input. RCLK is a free-running clock which can be

applied asynchronously to the analog input clock and can

operate up to 200MHz. The data output, DRDY signals and

EF flag are asserted synchronous to RCLK. See Section 1.7.

1.1.5.1 Dual-Edge Sampling

One ADC samples the input on the positive edge of the input

clock and the other ADC samples the same input on the

other edge of the input clock. The input is thus sampled twice

per input clock cycle, resulting in an overall sample rate of

twice the input clock frequency.

The ADC08B3000 uses dual edge sampling to achieve a

sampling frequency of 3 GSPS with a 1.5 GHz input clock.

The ADC08B3000 includes an automatic clock phase back-

ground calibration feature which automatically and continu-

ously adjusts the phase of the relative rising and falling edge

pahses. This feature removes the need to manually adjust

the clock phase and provides optimal ENOB performance

1.1.5.2 OutEdge Setting

To help ease data capture in the SDR mode, the output data

may be caused to transition on either the positive or the

negative edge of the Data Ready (DRDY) Pins. This is

chosen with the OutEdge input (pin 4). A high on the Out-

Edge input pin causes the output data to transition on the

rising edge of DRDY, while grounding this input causes the

output to transition on the falling edge of DRDY. See Section

2.4.3.

1.1.7 Power Down

The ADC08B3000 is in the active state when the Power

Down pin (PD) is low. When the PD pin is high, the device is

in the power down mode. In this power down mode the data

output pins (positive and negative) including DRDY and OR

+/- are put into a high impedance state and the devices

power consumption is reduced to a minimal level.

If the PD input is brought high while a calibration is running,

the device will not go into power down until the calibration

sequence is complete. However, if power is applied and PD

is already high, the device will not begin the calibration

sequence until the PD input goes low. If a manual calibration

is requested while the device is powered down, the calibra-

tion will not begin at all. That is, the manual calibration input

is completely ignored in the power down state.

1.2 NORMAL/EXTENDED CONTROL

The ADC08B3000 may be operated in one of two modes. In

the simpler standard control mode, the user affects available

configuration and control of the device through several con-

trol pins. The "extended control mode" provides additional

configuration and control options through a serial interface

and a set of 6 registers. The two control modes are selected

with pin 14 (FSR/ECE: Extended Control Enable). The

choice of control modes is required to be a fixed selection

and is not intended to be switched dynamically while the

device is operational.

Table 1 shows how several of the device features are af-

fected by the control mode chosen.

TABLE 1. Features and modes

Feature

Normal Control Mode

Extended Control Mode

RCLK Data transitions with rising or

falling RCLK edge

Selected with pin 4

Selected with the OE bit in the

Configuration Register

Power-On Calibration Delay

Delay Selected with pin 127

Short delay only.

Full-Scale Range

Options (600 mV

P-P or 800 mVP-P)

selected with pin 14. Selected range

applies to both channels.

Up to 512 step adjustments over a

nominal range of 560 mV to 840 mV.

Selected using register 3H

Input Offset Adjust

Not possible

±45 mV adjustments in 512 steps

using register 2h

Clock Phase Adjustment

Not possible

The clock phase can be adjusted

manually through the Coarse & Fine

registers (Eh and Dh)

Test Pattern

Not possible

A test pattern can be made present at

the data outputs by programming

register Fh.

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