DS3184N datasheet(11/389 Pages) MAXIM

Part #	DS3184N

Description	Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU

Download	389 Pages

Scroll/Zoom	100%

Manufacturer	MAXIM [Maxim Integrated Products]

Direct Link	https://www.maximintegrated.com/en.html

Logo

11 / 389 page

DS3181/DS3182/DS3183/DS3184

11 of 38

9

LIST OF TABLES

Table 4-1. Standards Compliance ............................................................................................................................. 23

Table 6-1. DS3/E3 ATM/Packet Mode Configuration Registers................................................................................ 26

Table 6-2. DS3/E3 ATM/Packet—OHM Mode Configuration Registers.................................................................... 27

Table 6-3. DS3/E3 Internal Fractional (IFRAC) ATM/Packet Mode Configuration Registers ................................... 28

Table 6-4. DS3/E3 External Fractional (XFRAC) ATM/Packet Mode Configuration Registers................................. 29

Table 6-5. DS3/E3 Flexible External Fractional (Subrate) Mode Configuration Registers........................................ 30

Table 6-6. DS3/E3 G.751 PLCP ATM Mode Configuration Registers ...................................................................... 31

Table 6-7. DS3/E3 G.751 PLCP ATM—OHM Mode Configuration Registers .......................................................... 32

Table 6-8. Clear-Channel ATM/Packet Mode Configuration Modes ......................................................................... 34

Table 6-9. Clear-Channel ATM/Packet—OHM Mode Configuration Registers......................................................... 35

Table 6-10. Clear-Channel Octet Aligned ATM/Packet—OHM Mode Configuration Registers ................................ 36

Table 7-1. HDB3/B3ZS/AMI LIU Mode Configuration Registers ............................................................................... 37

Table 7-2. HDB3/B3ZS/AMI Non-LIU Mode Configuration Registers ....................................................................... 39

Table 7-3. UNI Line Interface Mode Configuration Registers.................................................................................... 40

Table 7-4. UNI Line Interface—OHM Mode Configuration Registers........................................................................ 41

Table 8-1. DS3184 Short Pin Descriptions ................................................................................................................ 42

Table 8-2. Detailed Pin Descriptions ......................................................................................................................... 47

Table 9-1. Configuration of Global Register Settings ................................................................................................ 94

Table 9-2. Configuration of Port Register Settings .................................................................................................... 94

Table 10-1. LIU Enable Table.................................................................................................................................. 101

Table 10-2. All Possible Clock Sources Based on Mode and Loopback................................................................. 101

Table 10-3. Source Selection of TLCLK Clock Signal ............................................................................................. 102

Table 10-4. Source Selection of TCLKOn (internal TX clock) ................................................................................. 103

Table 10-5. Source Selection of RCLKO Clock Signal (internal RX clock) ............................................................. 103

Table 10-6. Transmit Line Interface Signal Pin Valid Timing Source Select........................................................... 104

Table 10-7. Transmit Framer Pin Signal Timing Source Select .............................................................................. 105

Table 10-8. Receive Line Interface Pin Signal Timing Source Select ..................................................................... 105

Table 10-9. Receive Framer Pin Signal Timing Source Select ............................................................................... 106

Table 10-10. Reset and Power-Down Sources ....................................................................................................... 109

Table 10-11. CLAD IO Pin Decode.......................................................................................................................... 112

Table 10-12. Global 8 kHz Reference Source Table............................................................................................... 113

Table 10-13. Port 8 kHz Reference Source Table................................................................................................... 113

Table 10-14. GPIO Global Signals .......................................................................................................................... 114

Table 10-15. GPIO Pin Global Mode Select Bits..................................................................................................... 114

Table 10-16. GPIO Port Alarm Monitor Select ........................................................................................................ 115

Table 10-17. Loopback Mode Selections ................................................................................................................ 117

Table 10-18. Line AIS Enable Modes ...................................................................................................................... 121

Table 10-19. Payload (downstream) AIS Enable Modes ........................................................................................ 122

Table 10-20. TSOFIn/TOHMIn Input Pin Functions ................................................................................................ 123

Table 10-21. TSERn/TPOHn/TFOHn Input Pin Functions ...................................................................................... 123

Table 10-22. TPDENIn/TPOHENn/TFOHENIn Input Pin Functions ....................................................................... 124

Table 10-23. TSOFOn/TDENn/TPOHSOFn/TFOHENOn Output Pin Functions .................................................... 124

Table 10-24. TCLKOn/TGCLKn/TPOHCLKn Output Pin Functions........................................................................ 125

Table 10-25. TPDATn Input Pin Functions .............................................................................................................. 125

Table 10-26. TPDENOn Output Pin Functions........................................................................................................ 125

Table 10-27. RSERn/RPOHn Output Pin Functions ............................................................................................... 126

Table 10-28. RPDENIn / RFOHENIn Input Pin Functions....................................................................................... 126

Table 10-29. RPDATn Input Pin Functions ............................................................................................................. 126

Table 10-30. RSOFOn/RDENn/RPOHSOFn/RFOHENOn Output Pin Functions................................................... 127

Table 10-31. RCLKOn/RGCLKn/RPOHCLKn Output Pin Functions ...................................................................... 127

Table 10-32. Framing Mode Select Bits FM[5:0] ..................................................................................................... 128

Table 10-33. Line Mode Select Bits LM[2:0]............................................................................................................ 134

Table 10-34. C-bit DS3 Frame Overhead Bit Definitions......................................................................................... 172

Table 10-35. M23 DS3 Frame Overhead Bit Definitions ......................................................................................... 175

Table 10-36. G.832 E3 Frame Overhead Bit Definitions ......................................................................................... 180

Table 10-37. Payload Label Match Status............................................................................................................... 183

Similar Part No. - DS3184N

Manufacturer	Part #	Datasheet	Description
Dallas Semiconductor	DS3184N	3Mb / 400P	Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU

More results

Similar Description - DS3184N

Manufacturer	Part #	Datasheet	Description
Dallas Semiconductor	DS3181	3Mb / 400P	Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU
Maxim Integrated Produc...	DS3184DK	2Mb / 23P	Quad ATM/Packet PHYs for DS3/E3/STS-1 with Built-In LIU Demo Kit REV: 060106
	DS3161	3Mb / 384P	Single/Dual/Triple/Quad ATM/Packet PHYs for DS3/E3/STS-1 REV: 113006
	DS34S101	1Mb / 13P	Single/Dual/Quad/Octal TDM-over-Packet Chip Rev: 101708
	DS34T101	1Mb / 16P	Single/Dual/Quad/Octal TDM-over-Packet Chip Rev: 101708
	DS34T101	803Kb / 74P	Single/Dual/Quad/Octal TDM-Over-Packet Chip Rev: 072707
	DS34T101	271Kb / 16P	Single/Dual/Quad/Octal TDM-over-Packet Chip Rev 6; 8/09
PMC-Sierra, Inc	PM7326-1	35Kb / 2P	ATM/PACKET Traffic Manager and Switch
Maxim Integrated Produc...	ICL7611ACPA	511Kb / 15P	Single/Dual/Triple/Quad Operational Amplifiers
Maxim Integrated Produc...	ICL7611DESA	517Kb / 26P	Single/Dual/Triple/Quad Operational Amplifiers Rev 3; 5/10

More results

DS3184N Datasheet(PDF) 11 Page - Maxim Integrated Products

DS3184N Datasheet(HTML) 11 Page - Maxim Integrated Products

Similar Part No. - DS3184N

Similar Description - DS3184N

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL