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ADSP-BF536BBCZ-4A Datasheet(PDF) 5 Page - Analog Devices |
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ADSP-BF536BBCZ-4A Datasheet(HTML) 5 Page - Analog Devices |
5 / 68 page ADSP-BF534/ADSP-BF536/ADSP-BF537 Rev. B | Page 5 of 68 | July 2006 The address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory manage- ment unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or SRAM, and larger, lower cost, and performance off-chip memory systems. See Figure 3. The on-chip L1 memory system is the highest performance memory available to the Blackfin processor. The off-chip mem- ory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 516M bytes of physical memory. The memory DMA controller provides high bandwidth data- movement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces. Internal (On-Chip) Memory The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have three blocks of on-chip memory providing high-bandwidth access to the core. The first block is the L1 instruction memory, consisting of 64K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed. The second on-chip memory block is the L1 data memory, con- sisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functional- ity. This memory block is accessed at full processor speed. The third memory block is a 4K byte scratchpad SRAM, which runs at the same speed as the L1 memories, but is only accessible as data SRAM, and cannot be configured as cache memory. External (Off-Chip) Memory External memory is accessed via the EBIU. This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The PC133-compliant SDRAM controller can be programmed to interface to up to 512M bytes of SDRAM. A separate row can be open for each SDRAM internal bank, and the SDRAM con- troller supports up to 4 internal SDRAM banks, improving overall performance. The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1M byte of memory. I/O Memory Space The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on- chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on- chip peripherals. |
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