 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADSP-BF539F Datasheet(PDF) 6 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADSP-BF539F Datasheet(HTML) 6 Page - Analog Devices |
|
|
6 / 68 page  Rev. PrF | Page 6 of 68 | September 2006 ADSP-BF539/ADSP-BF539F Preliminary Technical Data The second on-chip memory block is the L1 data memory, con- sisting of two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed. The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory. External (Off-Chip) Memory External memory is accessed via the EBIU. This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The PC133-compliant SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. The SDRAM con- troller allows one row to be open for each internal SDRAM bank, for up to four internal SDRAM banks, improving overall system performance. The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks will only be contiguous if each is fully popu- lated with 1M byte of memory. Flash Memory (ADSP-BF539F only) The ADSP-BF539F4 and ADSP-BF539F8 processors contain a separate flash die, connected to the EBIU bus, within the pack- age of the ADSP-BF539F processors. Figure 4 on Page 7 shows how the flash memory die and Blackfin processor die are connected. The ADSP-BF539F4 contains a 4 Mbit (256K x 16-bits) bottom boot sector flash memory. The ADSP-BF539F8 contains an 8 Mbit (512K x 16-bits) bottom boot sector flash memory. Fea- tures include the following. • access times as fast as 70 ns (EBIU registers be set appropriately) • sector protection • one million write cycles per sector • 20 year data retention The Blackfin processor connects to the flash memory die with address, data, chip enable, write enable, and output enable con- trols as if it were an external memory device. Figure 2. Blackfin Processor Core SEQUENCER ALIGN DECODE LOOP BUFFER 16 16 8 88 8 40 40 A0 A1 BARREL SHIFTER DATA ARITHMETIC UNIT CONTROL UNIT R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.H R0.L ASTAT 40 40 32 32 32 32 32 32 32 LD0 LD1 SD DAG0 DAG1 ADDRESS ARITHMETIC UNIT I3 I2 I1 I0 L3 L2 L1 L0 B3 B2 B1 B0 M3 M2 M1 M0 SP FP P5 P4 P3 P2 P1 P0 DA1 DA0 32 32 32 PREG RAB 32 |
Similar Part No. - ADSP-BF539F |
|
Similar Description - ADSP-BF539F |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
