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NB2305AC1HDTG Datasheet(PDF) 5 Page - ON Semiconductor |
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NB2305AC1HDTG Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 8 page NB2305A http://onsemi.com 5 Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input−output delay. For applications requiring zero input−output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero−input−output delay. SWITCHING WAVEFORMS Figure 3. Duty Cycle Timing 1.4 V 1.4 V 1.4 V t1 t2 Figure 4. All Outputs Rise/Fall Time t3 OUTPUT 2.0 V 0.8 V t4 2.0 V 0.8 V 3.3 V 0 V 1.4 V 1.4 V t5 Figure 5. Output − Output Skew OUTPUT OUTPUT t6 INPUT OUTPUT Figure 6. Input − Output Propagation Delay VDD 2 VDD 2 Figure 7. Device − Device Skew t7 CLKOUT, Device 1 VDD 2 VDD 2 CLKOUT, Device 2 |
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