NB4N840M

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3

Table 2. PIN DESCRIPTION

Pin

Name

I/O

Description

1

ENB1

LVTTL

Channel B1 Output Enable. LVTTL low input powers down B1 output stage.

2

DB1

CML Input

Channel B1 Positive Signal Input

3

DB1

CML Input

Channel B1 Negative Signal Input

4

ENB0

LVTTL

Channel B0 Output Enable. LVTTL low input powers down B0 output stage.

5

SELB0

LVTTL

Channel B0 Output Select. See Table 1.

6

DB0

CML Input

Channel B0 Positive Signal Input

7

DB0

CML Input

Channel B0 Negative Signal Input

8

SELB1

LVTTL

Channel B1 Output Select. See Table 1.

9,24

GND

−

Supply Ground. All GND pins must be externally connected to power supply to guarantee

proper operation.

10, 13, 16,

17, 20, 23

−

proper operation.

11

QB0

CML Output

Channel B0 Negative Output.

12

QB0

CML Output

Channel B0 Positive Output.

14

QB1

CML Output

Channel B1 Negative Output.

15

QB1

CML Output

Channel B1 Positive Output.

18

QA1

CML Output

Channel A1 Negative Output.

19

QA1

CML Output

Channel A1 Positive Output.

21

QA0

CML Output

Channel A0 Negative Output.

22

QA0

CML Output

Channel A0 Positive Output.

25

SELA1

LVTTL

Channel A1 Output Select, LVTTL Input. See Table 1.

26

DA0

CML Input

Channel A0 Positive Signal Input.

27

DA0

CML Input

Channel A0 Negative Signal Input.

28

SELA0

LVTTL

Channel A0 Output Select, LVTTL Input. See Table 1.

29

ENA0

LVTTL

Channel A0 Output Enable. LVTTL low input powers down A0 output stage.

30

DA1

CML Input

Channel A1 Positive Signal Input.

31

DA1

CML Input

Channel A1 Negative Signal Input.

32

ENA1

LVTTL

Channel A1 Output Enable. LVTTL low input powers down A1 output stage.

−

EP

GND

Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing)

must be attached to a heat−sinking conduit. The exposed pad must be soldered to the

circuit board GND for proper electrical and thermal operation.