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NB4N441MNG Datasheet(PDF) 8 Page - ON Semiconductor |
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NB4N441MNG Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 12 page NB4N441 http://onsemi.com 8 Figure 4. Power Supply Filter PLL_VCC VCC 0.01 mF 47 mF L=1000 mH R=15 W 0.01 mF 3.3 V or 5.0 V RS = 5 W 3.3 V or 5.0 V Power Supply Filtering The NB4N441 is a mixed analog/digital product and as such, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The NB4N441 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (PLL_VCC) of the device. The purpose of this design technique is to try and isolate the high switching noise of the digital outputs from the relatively sensitive internal analog phase−locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simplest form of isolation is a power supply filter on the PLL_VCC Pin for the NB4N441. Figure 4 illustrates a typical power supply filter scheme. The NB4N441 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the PLL_VCC pin of the NB4N441. From the data sheet, the PLL_VCC current (the current sourced through the PLL_VCC Pin) is typically 26 mA. Assuming that a minimum of 2.9 V must be maintained on the PLL_VCC pin, very little DC voltage drop can be tolerated when a 3.3 V VCC supply is used. The resistor shown in Figure 4 must have a resistance of 5 W Max to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor, it’s overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. The level of required filtering is subject to further optimization and simplification. All the VCC pins are connected to the same VCC plane. All the ground pins (GND) are connected to the same GND plane. |
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