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MP8830 Datasheet(PDF) 4 Page - Exar Corporation |
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MP8830 Datasheet(HTML) 4 Page - Exar Corporation |
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4 / 20 page  MP8830 4 Rev. 1.00 ELECTRICAL CHARACTERISTICS Unless otherwise specified: AVDD = DVDD= 5 V, DGND = AGND = 0 V, VREF = AVDD 0.2 Temperature = 0 to 60 °C1 A/D Converters Parameter Symbol Min Typ Max Units Test Conditions/Comments Resolution N 10 Bits Differential Non-Linearity DNL –1 0.75 2 LSB Gain DAC = 000 (hex), offset DAC = 00 (hex). Monotonicity guaranteed. Differential Non-Linearity DNL –1 0.5 2 LSB Gain DAC = 1FF (hex), offset DAC = 00 (hex). Monotonicity guaranteed. Integral Non-Linearity INL 2 2.75 LSB Gain DAC = 000 (hex), offset DAC = 00 (hex), Best fit straight line. Integral Non-Linearity INL 1.5 2 LSB Gain DAC = 1FF (hex), offset DAC = 00 (hex), Best fit straight line. Zero Scale Error ZSE –15 9 mV Measured with offset and gain DACs set to 000. Offset is defined as the difference be- tween the clamp voltage and the analog input voltage which results in the transition of the ADC code from 004 to 005. Zero Scale Drift2 ZSD 50 µV/°C Measured as the change in the ZSE over tem- perature. This error does not include the error introduced by the external VREF amplifier or external VREF resistor divider. DC Input Range AIN VCLP –5mV 2.92 V + VCLP –5 mV V The digitizing range is set with the Gain DAC and offset DAC. Please note AIN (min) is VCLP – 4 LSB = VRB and AIN (max) is GFS (max) + ZSR (max) + VCLP – 4 LSB. Data Rate FS 1.25 MSPS The conversion rate is determined by the tim- ing diagram and timing specifications. Set by the CVL period. Analog Input Voltage Change from Sample to Sample2 DAIN 0 FS V Assuming AIN voltage remains within the spe- cified digitizing range based on the offset and gain DAC codes. Input Capacitance2 CIN 45 pF Measured with AIN DC = 2.5 V and AENL = low. Gain DAC Resolution N 9 Bits Differential Non-Linearity DNL –1 +2.25 LSB Integral Non-Linearity INL +2 LSB Gain DAC Full Scale (VRT – VRB) GFS 2.6 2.68 2.76 V Gain DAC = 1FF VRT is the top of the ADC reference ladder. Refer to block diagram. Gain DAC Zero Scale (VRT – VRB) GZS 1.22 1.26 1.3 V Gain DAC = 000 VRB is the bottom of the ADC reference lad- der. Refer to block diagram. Maximum Gain Change per Cycle2 MGC 50 % FSR After the specified maximum change in gain DAC setting, the ADC should output the same code 1 LSB for all of the following conver- sions assuming the analog input remains fixed, i.e. DC. Settling Time (MGC)2 ts-gd 200 ns |
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