4

SY89312V

Micrel, Inc.

M9999-051006

hbwhelp@micrel.com or (408) 955-1690

TIMING DIAGRAM

Q

CLK

t

RR

RESET

PECL: V

T

Symbol

Parameter

Condition

Min

Typ

Max

Units

f

MAX

Maximum Input Frequency

4

——

GHz

t

pd

Propagation Delay to Output

ps

Differential

RESET, CLK ➝ Q, /Q

250

275

440

t

RR

Set/Reset Recovery

200

100

—

ps

t

PW

Minimum Pulse Width

RESET

550

200

—

ps

t

JITTER

Cycle-to-Cycle RMS Jitter

——

1ps

RMS

V

PP

Input Voltage Swing

150

800

1200

mV

(Differential)

t

r

Output Rise/Fall Times

Q, /Q

50

100

160

ps

t

f

(20% to 80%)

Note:

6. Measured using a 750mV source, 50% duty cycle clock source.