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ADATE205BSV Datasheet(PDF) 1 Page - Analog Devices |
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ADATE205BSV Datasheet(HTML) 1 Page - Analog Devices |
1 / 16 page 250 MHz Dual DCL ADATE205 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. FEATURES Driver, comparator, and active load 250 MHz toggle rate Inhibit mode function Dynamic clamps Operating voltage range: −1.5 V to +6.5 V Output voltage swing: 200 mV to 8 V Four range adjustable slew rate True/complement data mode bit 100-lead thin quad flat package, exposed pad Low per channel power 1.15 W with load off 1.50 W with load programmed at 20 mA nominal Low leakage (<10 nA) in High-Z mode Driver 50 Ω output resistance 1.6 ns minimum pulse width for a 3 V step Load: −35 mA to +35 mA maximum current range APPLICATIONS Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment GENERAL DESCRIPTION The ADATE205 is a complete, single-chip solution that performs the pin electronics functions of driver, comparator, and active load (DCL) for ATE applications. The active load can be powered down if not used. The driver is a proprietary design that features three active modes: data high mode, data low mode, and term mode, as well as an inhibit state. The driver has low leakage (<10 nA) in High-Z mode. The output voltage range is −1.5 V to +6.5 V to accommodate a wide variety of test devices. The ADATE205 supports four programmable Tr/Tf times for applications where slower edge rates are required. The edge rate selection is done via two static digital CMOS select bits. The input data to the driver can be inverted using a single CMOS logic bit. This feature can be used for system calibration or applications where complement input data is needed. FUNCTIONAL BLOCK DIAGRAM DRIVER VCC (18, 19, 57, 58, 77, 78, 89, 98, 99) 1x COMP_H IOL IOH TEMP GNDREF VIOH VIOL VCOM CVL COMP_L_N COMP_H_N COMP_H_P CVH LDEN VTEN DR_EN_N DR_EN_N_T DR_EN_P_T DR_EN_P DR_DATA_N DR_DATA_N_T DR_DATA_P_T DR_DATA_P DR_INV VIH VIL VIT COMP_L_P CLLM DUT CLAMPH CLAMPL TEMP SENSOR (5 DIODES) LOGIC LOAD LOGIC 7 69 8 68 9 67 6 70 81 95 88 11 66 10 65 22 54 23 53 24 52 25 51 26 50 27 49 28 48 29 47 15 61 14 62 4 72 3 73 2 74 31 45 91 85 32 44 13 63 COMP_L 34 42 35 41 90 86 1 75 NC (30, 46) SHIELDS (80, 82, 94, 96) ADATE205 VEE (16, 17, 33, 43, 59, 60, 84, 87, 92) GND (5, 12, 20, 21, 36, 40, 55, 56, 64, 71, 76, 79, 83, 93, 97,100) Figure 1. |
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