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CY7C006
CY7C016
8
Notes:
19. BUSY = HIGH for the writing port.
20. CEL = CER = LOW.
21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the
specified tPWE.
23. R/W must be HIGH during all address transitions.
Switching Waveforms (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/W R
DATA INR
DATAOUTL
C006-12
tWC
ADDRESSR
t
PWE
VALID
t
SD
t
HD
ADDRESSL
Read Timing with Port-to-Port Delay (M/S=L)[19, 20]
C006-13
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA
tPWE
tHD
tSD
tHA
tHZOE
t
LZOE
SEM OR CE
R/W
ADDRESS
OE
DATA OUT
DATA IN
Write Cycle No. 1: OE Three-State Data I/Os (Either Port)[21, 22, 23]
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