2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 – Rev. 6/98

©1998, Micron Technology, Inc.

2

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

PART NUMBERS

EDO Operating Mode

PART NUMBER

CONFIGURATION

SPEED

MT9LD272AG-5 X

2 Meg x 72 ECC

50ns

MT9LD272AG-6 X

2 Meg x 72 ECC

60ns

MT18LD472AG-5 X

4 Meg x 72 ECC

50ns

MT18LD472AG-6 X

4 Meg x 72 ECC

60ns

FPM Operating Mode

PART NUMBER

CONFIGURATION

SPEED

MT9LD272AG-6

2 Meg x 72 ECC

60ns

MT18LD472AG-6

4 Meg x 72 ECC

60ns

EDO PAGE MODE

EDO PAGE MODE, designated by the “X” version, is an

accelerated FAST-PAGE-MODE cycle. The primary advan-

tage of EDO is the availability of data-out even after CAS#

goes back HIGH. EDO provides for CAS# precharge time

elimination of CAS# output control provides for pipelined

READs.

FAST-PAGE-MODE modules have traditionally turned

the output buffers off (High-Z) with the rising edge of

CAS#. EDO-PAGE-MODE DRAMs operate like FAST-

PAGE-MODE DRAMs, except data will remain valid or

become valid after CAS# goes HIGH during READs, pro-

vided RAS# and OE# are held LOW. If OE# is pulsed while

RAS# and CAS# are LOW, data will toggle from valid data

to High-Z and back to the same valid data. If OE# is toggled

or pulsed after CAS# goes HIGH while RAS# remains

LOW, data will transition to and remain High-Z.

During an application, if the DQ outputs are wire OR’d,

OE# must be used to disable idle banks of DRAMs. Alterna-

tively, pulsing WE# to the idle banks during CAS# HIGH

time will also High-Z the outputs. Independent of OE#

enced from the rising edge of RAS# or CAS#, whichever

occurs last. (Refer to the 4 Meg x 4 [MT4LC4M4E8] DRAM

data sheet for additional information on EDO functional-

ity.)

REFRESH

Returning RAS# and CAS# HIGH terminates a memory

cycle and decreases chip current to a reduced standby level.

Also, the chip is preconditioned for the next cycle during

the RAS# HIGH time. Correct memory cell data is pre-

served by maintaining power and executing any RAS#

cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-

ONLY, CBR or HIDDEN) so that all combinations of RAS#

regardless of sequence. The CBR REFRESH cycle will in-

voke the internal refresh counter for automatic RAS# ad-

dressing.

SERIAL PRESENCE-DETECT OPERATION

This module family incorporates serial presence-detect

(SPD). The SPD function is implemented using a 2,048-bit

EEPROM. This nonvolatile storage device contains 256

bytes. The first 128 bytes can be programmed by Micron to

identify the module type and various DRAM organizations

and timing parameters. The remaining 128 bytes of storage

are available for use by the customer. System READ/

WRITE operations between the master (system logic) and

the slave EEPROM device (DIMM) occur via a standard IIC

bus using the DIMM’s SCL (clock) and SDA (data) signals,

GENERAL DESCRIPTION

The MT9LD272A(X) and MT18LD472A(X) are randomly

accessed 16MB and 32MB memories organized in a x72

configuration. They are specially processed to operate from

3V to 3.6V for low-voltage memory systems.

During READ or WRITE cycles, each bit is uniquely

addressed through the 21/22 address bits, which are en-

tered 11 bits (A0 -A10) at RAS# time and 10/11 bits (A0-

A10) at CAS# time.

READ and WRITE cycles are selected with the WE#

input. A logic HIGH on WE# dictates read mode, while a

logic LOW on WE# dictates write mode. During a WRITE

cycle, data-in (D) is latched by the falling edge of WE# or

CAS#, whichever occurs last. An EARLY WRITE occurs

when WE# is taken LOW prior to CAS# falling. A LATE

WRITE or READ-MODIFY-WRITE occurs when WE# falls

after CAS# was taken LOW. During EARLY WRITE cycles,

the data-outputs (Q) will remain High-Z regardless of the

state of OE#. During LATE WRITE or READ-MODIFY-

WRITE cycles, OE# must be taken HIGH to disable the data-

outputs prior to applying input data. If a LATE WRITE or

READ-MODIFY-WRITE is attempted while keeping OE#

LOW, no WRITE will occur, and the data-outputs will drive

read data from the accessed location.

FAST PAGE MODE

FAST-PAGE-MODE operations allow faster data opera-

tions (READ or WRITE) within a row-address-defined

page boundary. The FAST-PAGE-MODE cycle is always

initiated with a row address strobed in by RAS#, followed

by a column address strobed in by CAS#. Additional col-

umns may be accessed by providing valid column

addresses, strobing CAS# and holding RAS# LOW , thus

executing faster memory cycles. Returning RAS# HIGH

terminates the FAST-PAGE-MODE operation.