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TPS62401DRC Datasheet(PDF) 3 Page - Texas Instruments |
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TPS62401DRC Datasheet(HTML) 3 Page - Texas Instruments |
3 / 39 page www.ti.com ELECTRICAL CHARACTERISTICS TPS62400 ,, TPS62401 TPS62403 SLVS681C – JUNE 2006 – REVISED DECEMBER 2006 V IN = 3.6V, VOUT = 1.8V, EN = VIN, MODE = GND, L = 2.2µH, COUT = 20µF, TA = –40°C to 85°C typical values are at TA = 25 °C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VIN Input voltage range 2.5 6.0 V One converter, IOUT = 0mA. PFM mode 19 29 µA enabled (Mode = 0) device not switching, EN1 = 1 OR EN2 = 1 Two converter, IOUT = 0mA. PFM mode 32 48 µA enabled (Mode = 0) device not switching, IQ Operating quiescent current EN1 = 1 AND EN2 = 1 IOUT = 0mA, MODE/DATA = GND, for one 23 µA converter, VOUT 1.575V(1) IOUT = 0mA, MODE/DATA = VIN, for one 3.6 mA converter, VOUT 1.575V (1) EN1, EN2 = GND, VIN = 3.6V(2) 1.2 3 ISD Shutdown current µA EN1, EN2 = GND, VIN ramped from 0V to 0.1 1 3.6V(3) Falling 1.5 2.35 VUVLO Undervoltage lockout threshold V Rising 2.4 ENABLE EN1, EN2 VIH High-level input voltage, EN1, EN2 1.2 VIN V VIL Low-level input voltage, EN1, EN2 0 0.4 V IIN Input bias current, EN1, EN2 EN1, EN2 = GND or VIN 0.05 1.0 µA DEF_1 INPUT VDEF_1H DEF_1 high level input voltage DEF_1 pin is a digital input at TPS62401 0.9 VIN V fixed output voltage option VDEF_1L DEF_1 low level input voltage DEF_1 pin is a digital input at TPS62401 0 0.4 V fixed output voltage option IIN Input bias current DEF_1 DEF_1 GND or VIN 0.01 1.0 µA MODE/DATA VIH High-level input voltage, MODE/DATA 1.2 VIN V VIL Low-level input voltage, MODE/DATA 0 0.4 V IIN Input bias current, MODE/DATA MODE/DATA = GND or VIN 0.01 1.0 µA VOH Acknowledge output voltage high Open drain, via external pullup resistor VIN V VOL Acknowledge output voltage low Open drain, sink current 500 µA 0 0.4 V INTERFACE TIMING tStart Start time 2 µs tH_LB High time low bit, logic 0 detection Signal level on MODE/DATA pin is > 1.2V 2 200 µs tL_LB Low time low bit, logic 0 detection Signal level on MODE/DATA pin < 0.4V 2x 400 µs tH_LB tL_HB Low time high bit, logic 1 detection Signal level on MODE/DATA pin < 0.4V 2 200 µs tH_HB High time high bit, logic 1 detection Signal level on MODE/DATA pin is > 1.2V 2x 400 µs tL_HB TEOS End of Stream TEOS 2 µs tACKN Duration of acknowledge condition VIN 2.5V to 6V 400 520 µs (MODE/DATE line pulled low by the device) tvalACK Acknowledge valid time 2 µs (1) Device is switching with no load on the output, L = 3.3 µH, value includes losses of the coil (2) These values are valid after the device has been already enabled one time (EN1 or EN2 = high) and supply voltage VIN has not powered down. (3) These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage VIN is powered up. The values remain valid until the device has been enabled first time (EN1 or EN2 = high). After first enable, Note 3 becomes valid. 3 Submit Documentation Feedback |
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