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IDT8535-01 Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT8535-01 Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 11 page 8 COMMERCIALANDINDUSTRIALTEMPERATURERANGES IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL APPLICATION INFORMATION TERMINATION FOR LVPECL OUTPUTS TheclocklayouttopologyshownbelowisatypicalterminationforLVPECLoutputs. Thetwodifferentlayoutsmentionedarerecommendedonlyasguidelines. FOUTandxFOUTarelowimpedancefolloweroutputsthatgenerateECL/LVPECLcompatibleoutputs. Therefore,terminatingresistors(DCcurrent pathto ground)orcurrentsourcesmustbeusedforfunctionality. Theseoutputsaredesignedtodrive50 Ωtransmissionlines. Matchedimpedancetechniquesshould be used to maximize operating frequency and minimize signal distortion. The diagrams below show two different layouts which are recommended only as guidelines. Othersuitableclocklayoutsmayexist. Itisrecommendedthattheboarddesignerssimulatetoguaranteecompatibilityacrossallprintedcircuitand clockcomponentprocessvariations. LVPECL Output Termination, layout A LVPECL Output Termination, layout B FOUT 50 Ω 50 Ω Zo = 50 Ω VDD - 2V Zo = 50 Ω RTT FIN RTT = (VOH + VOL / VDD - 2) - 2 1 Zo FOUT Zo = 50 Ω Zo = 50 Ω FIN Zo 3 2 Zo 3 2 Zo 5 2 Zo 5 2 3.3V |
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