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MAX1303AEUP Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX1303AEUP Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 31 page 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs _______________________________________________________________________________________ 5 ELECTRICAL CHARACTERISTICS (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Preamplifier Supply Voltage AVDD2 4.75 5.25 V Digital I/O Supply Voltage DVDDO 2.70 5.25 V Internal reference 3 3.5 AVDD1 Supply Current IAVDD1 External clock mode, external acquisition mode, or internal clock mode External reference 2.5 3 mA DVDD Supply Current IDVDD External clock mode, external acquisition mode, or internal clock mode 0.9 2 mA AVDD2 Supply Current IAVDD2 External clock mode, external acquisition mode, or internal clock mode 17.5 25 mA DVDDO Supply Current IDVDDO External clock mode, external acquisition mode, or internal clock mode 0.2 1 mA Partial power-down mode 1.3 mA Total Supply Current Full power-down mode 2 µA Power-Supply Rejection Ratio PSRR All analog input ranges ±0.5 LSB TIMING CHARACTERISTICS (Figures 15 and 16) External clock mode 272 62 External acquisition mode 228 62 SCLK Period tCP Internal clock mode 100 83 µs External clock mode 109 External acquisition mode 92 SCLK High Pulse Width (Note 5) tCH Internal clock mode 40 ns External clock mode 109 External acquisition mode 92 SCLK Low Pulse Width (Note 5) tCL Internal clock mode 40 ns DIN to SCLK Setup tDS 40 ns DIN to SCLK Hold tDH 0ns SCLK Fall to DOUT Valid tDO 40 ns CS Fall to DOUT Enable tDV 40 ns |
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