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EM25LV512-33MS Datasheet(PDF) 9 Page - ELAN Microelectronics Corp |
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EM25LV512-33MS Datasheet(HTML) 9 Page - ELAN Microelectronics Corp |
9 / 30 page EM25LV512 512 K (64K x 8) Bits Serial Flash Memory SPECIFICATION If Chip Select (S#) goes High while the device is in the Hold condition, the internal logic of the device will be reset. To restart communication with the device, it is necessary to drive Hold (HOLD#) to High, and then drive Chip Select (S#) to Low. This prevents the device from going back to the Hold condition. Write Protect The EM25LV512 offers the following data protection mechanism features to prevent inadvertent write from noisy environment: Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase, and Write Status Register instructions consisting of a number of clock pulses in multiple of eight, will be checked before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: • Power-up • Write Disable (WRDI) instruction completion • Write Status Register (WRSR) instruction completion • Page Program (PP) instruction completion • Block Erase (BE) instruction completion • Chip Erase (CE) instruction completion The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W#) signal, in collaboration with the Status Register Write Disable (SRWD) bit, allows the Block Protect (BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be write-protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write from Program and Erase because all instructions are ignored except one particular instruction (the Release from Deep Power down instruction). The protection features of the device are summarized in the following table (Table 6). When the Status Register Write Disable (SRWD) bit of the Status Register is set at “0” (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of whether Write Protect (W#) is driven High or Low. This specification is subject to change without further notice. (11.08.2004 V1.0) Page 9 of 30 |
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