Electronic Components Datasheet Search |
|
TPS54615-Q1 Datasheet(PDF) 11 Page - Texas Instruments |
|
TPS54615-Q1 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 18 page TPS54611Q1,TPS54612Q1 TPS54613Q1,TPS54614Q1 TPS54615Q1,TPS54616Q1 SGLS266D − OCTOBER 2004 − REVISED DECEMBER 2004 www.ti.com 11 GROUNDING AND POWERPAD LAYOUT The TPS54611−16 have two internal grounds (analog and power). Inside the TPS54611−16, the analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD is tied internally to the analog ground. Noise injected between the two grounds can degrade the performance of the TPS54611−16, particularly at higher output currents. However, ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground planes are recommended. These two planes should tie together directly at the IC to reduce noise between the two grounds. The only components that should tie directly to the power ground plane are the input capacitor, the output capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54611−16. The layout of the TPS54614 evaluation module is representative of a recommended layout for a 4-layer board. Documentation for the TPS54614 evaluation module can be found on the Texas Instruments web site (www.ti.com) under the TPS54614 product folder. See the TPS54614−185 User’s Guide, Texas Instruments (SLVU053) and the application note, Texas Instruments (SLVA105). LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection from the exposes area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the 10 recommended that enhance thermal performance should be included in areas not under the device package. Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance Minimum Recommended Top Side Analog Ground Area 0.3478 0.0150 0.06 0.0256 0.1700 0.1340 0.0630 0.0400 Ø 0.0180 4 PL 0.2090 Ø 0.0130 8 PL Minimum Recommended Exposed Copper Area for Powerpad. 5mm Stencils May Require 10 Percent Larger Area 0.0650 0.0500 0.0500 0.0650 0.0339 0.0339 0.0500 Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside Powerpad Area 4 x 0.018 Diameter Under Device as Shown. Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground Area Is Extended. 0.3820 Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD |
Similar Part No. - TPS54615-Q1 |
|
Similar Description - TPS54615-Q1 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |