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START

STOP

1

0

1

0

1

1

SDA

SCK

T0077-01

REGISTER MAPPING

ONET1191V

SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006

Figure 3. Two-Wire Interface Timing Diagram

Table 1. Two-Wire Interface Timing

PARAMETER

DESCRIPTION

MIN MAX

UNIT

START hold time

Time required from data falling edge to clock falling edge at START

10

ns

Clock and data rise time

Clock and data rise time

10

ns

Clock and data fall time

Clock and data fall time

10

ns

Clock high time

Minimum clock high period

50

ns

Data high time

Minimum data high period

100

ns

Data setup time

Minimum time from data rising edge to clock rising edge

10

ns

Data wait time

Minimum time from data falling edge to data rising edge

50

ns

Data hold time

Minimum time from clock falling edge to data falling edge

10

ns

STOP setup time

Minimum time from clock rising edge to data rising edge at STOP

10

ns

The register mapping for the register addresses 0 (000b) through 3 (011b) are shown in Table 2 through

Table 5. Table 6 describes the circuit functionality based on the register settings.

Table 2. Register 0 (000b) Mapping

address 0 (000b)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

ENA

PDP

PDR

OLE

FLTEN

MODR

EQENB

–

Table 3. Register 1 (001b) Mapping

address 1 (001b)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

MODC7

MODC6

MODC5

MODC4

MODC3

MODC2

MODC1

MODC0

5

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