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S29WS128N0LBFI113 Datasheet(PDF) 3 Page - SPANSION

Part # S29WS128N0LBFI113
Description  256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S29WS128N0LBFI113 Datasheet(HTML) 3 Page - SPANSION

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October 29, 2004 S29WSxxxN_00_F0
S29WSxxxN MirrorBit™ Flash Family
3
Pre l i m i n a r y
List of Figures
Figure 4.2. VBH084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package.......................................................... 10
Figure 4.3. 80-ball Fine-Pitch Ball Grid Array (S29WS064N) .................................................................................................................... 11
Figure 4.4. TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm MCP Compatible Package ............................................................... 12
Figure 4.5. MCP Look-ahead Diagram................................................................................................................................................... 14
Figure 7.2. Synchronous Read............................................................................................................................................................. 24
Figure 7.19. Single Word Program....................................................................................................................................................... 30
Figure 7.22. Write Buffer Programming Operation ................................................................................................................................. 34
Figure 7.24. Sector Erase Operation.................................................................................................................................................... 37
Figure 7.33. Write Operation Status Flowchart...................................................................................................................................... 44
Figure 8.2. Lock Register Program Algorithm......................................................................................................................................... 55
Figure 11.2. Maximum Positive Overshoot Waveform.............................................................................................................................. 62
Figure 11.3. Test Setup ...................................................................................................................................................................... 63
Figure 11.4. Input Waveforms and Measurement Levels.......................................................................................................................... 64
Figure 11.5. VCC Power-up Diagram ..................................................................................................................................................... 64
Figure 11.6. CLK Characterization ........................................................................................................................................................ 66
Figure 11.7. CLK Synchronous Burst Mode Read .................................................................................................................................... 68
Figure 11.8. 8-word Linear Burst with Wrap Around ............................................................................................................................... 69
Figure 11.9. 8-word Linear Burst without Wrap Around........................................................................................................................... 69
Figure 11.10. Linear Burst with RDY Set One Cycle Before Data ............................................................................................................... 70
Figure 11.11. Asynchronous Mode Read................................................................................................................................................ 71
Figure 11.12. Reset Timings................................................................................................................................................................ 72
Figure 11.2. Chip/Sector Erase Operation Timings: WE# Latched Addresses ............................................................................................. 74
Figure 11.13. Asynchronous Program Operation Timings: WE# Latched Addresses ..................................................................................... 75
Figure 11.14. Synchronous Program Operation Timings: CLK Latched Addresses ........................................................................................ 76
Figure 11.15. Accelerated Unlock Bypass Programming Timing ................................................................................................................ 77
Figure 11.16. Data# Polling Timings (During Embedded Algorithm) .......................................................................................................... 77
Figure 11.17. Toggle Bit Timings (During Embedded Algorithm) ............................................................................................................... 78
Figure 11.18. Synchronous Data Polling Timings/Toggle Bit Timings ......................................................................................................... 78
Figure 11.19. DQ2 vs. DQ6 ................................................................................................................................................................. 79
Figure 11.20. Latency with Boundary Crossing when Frequency > 66 MHz................................................................................................. 79
Figure 11.21. Latency with Boundary Crossing into Program/Erase Bank ................................................................................................... 80
Figure 11.22. Example of Wait States Insertion ..................................................................................................................................... 81
Figure 11.23. Back-to-Back Read/Write Cycle Timings ............................................................................................................................ 82


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