4V to 72V Input LDOs with Boost Preregulator

4

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ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

ENABLE, HOLD and RESET

EN High Input Threshold

2.4

V

EN Low Input Threshold

0.4

V

EN Input Bias Current

0.25

2

µA

HOLD Low Input Threshold

Regulator on, EN transition from high to low

0.4

V

HOLD Release Voltage

EN = low

0.4

V

HOLD Pullup Current

Internally connected to OUT

4

µA

RESET Voltage Threshold

87

90

92

%

RESET Threshold Hysteresis

2%

RESET Output Low Voltage

0.4

V

RESET Output High Leakage

Current

1

µA

RESET Output Minimum Timeout

Period

25

µs

EN to RESET Minimum Timeout

Delay

260

µs

Delay Comparator Threshold

(Rising)

1.205

1.24

1.265

V

Delay Comparator Threshold

Hysteresis

100

mV

CT Charge Current

1.5

2

2.5

µA

CT Discharge Current

5mA

Note 2: Limits at -40°C are guaranteed by design and characterization; not production tested.

Note 4: Guaranteed by design and not production tested.

Note 5: The continuous maximum output current from the LDO is guaranteed according to the maximum power dissipation imposed

by the package thermal constraints.

Note 6: Maximum output adjustable value is conditioned by the maximum adjustable BSOUT Output Voltage Range minus the maxi-

mum dropout across the pass transistor.