S70WS512N00BFWA32 datasheet(11/93 Pages) SPANSION

Part #	S70WS512N00BFWA32

Description	Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory

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Manufacturer	SPANSION [SPANSION]

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March 14, 2005 S70WS512N00_00_A0

S70WS512N00 Based MCPs

9

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Information

3

Input/Output Descriptions

Table 3.1 identifies the input and output package connections provided on the device.

Table 3.1 Input/Output Descriptions

Symbol

Description

A23-A0

Address inputs

DQ15-DQ0

Data input/output

OE#

Output Enable input. Asynchronous relative to CLK for the Burst mode.

WE#

Write Enable input.

VSS

Ground

NC

No Connect; not connected internally

RDY

Ready output. Indicates the status of the Burst read.

CLK

Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment

the internal address counter. Should be at VIL or VIH while in asynchronous mode

AVD#

Address Valid input. Indicates to device that the valid address is present on the address inputs.

Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be

latched.

High = device ignores address inputs

F-RST#

Hardware reset input. Low = device resets and returns to reading array data

F-WP#

Hardware write protect input. At VIL, disables program and erase functions in the four outermost

sectors. Should be at VIH for all other conditions.

F-ACC

Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass

mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions.

F1-CE#

Chip-enable input for Flash 1. Asynchronous relative to CLK for Burst Mode.

F2-CE#

Chip-enable input for Flash 2. Asynchronous relative to CLK for Burst Mode.

F-VCC

Flash 1.8 Volt-only single power supply.

DNU

Do Not Use

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