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PCI2030 Datasheet(PDF) 10 Page - Texas Instruments |
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PCI2030 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 14 page PCI2030 PCI-TO-PCI BRIDGE XCPS012 – DECEMBER 1997 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER SIDE TEST CONDITIONS OPERATION MIN MAX UNIT VOH High le el o tp t oltage IOH = –0.5 mA 3.3 V 0.9 VCC V VOH High-level output voltage IOH = –2 mA 5 V 2.4 V VOL Low level output voltage IOL = 1.5 mA 3.3 V 0.1 VCC V VOL Low-level output voltage IOL = 6 mA 5 V 0.55 V Input pins VV † 3.6 V 10 IIH High level input current Input pins VI = VCC† 5.25 V 20 µA IIH High-level input current I/O pins‡ VV † 3.6 V 20 µA I/O pins‡ VI = VCC† 5.25 V 25 I Low level input current Input pins VI = GND 3.6 V to 5.25 V –1 A IIL Low-level input current I/O pins‡ VI = GND 3.6 V to 5.25 V –20 µA IOZ High-impedance output current VO = VCCP or GND ±20 µA † For PCI pins, VCC = VCCP. ‡ For I/O pins, the input leakage current includes the off-state output current IOZ. PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 1, Figure 2, and Figure 3) ALTERNATE SYMBOL MIN MAX UNIT tc Cycle time, PCLK tcyc 30 ∞ ns twH Pulse duration, PCLK high thigh 11 ns twL Pulse duration, PCLK low tlow 11 ns ∆v/∆t Slew rate, PCLK tr, tf 1 4 V/ns tw Pulse duration, RSTIN trst 1 ms tsu Setup time, PCLK active at end of RSTIN (see Note 3) trst-clk 100 ms NOTE 3: The setup and hold times for the secondary are identical to those for the primary; however, the times are relative to the secondary PCI close. PCI timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4 and Figure 1 and Figure 4) ALTERNATE SYMBOL TEST CONDITIONS MIN MAX UNIT t d Propagation delay time PCLK to shared signal valid delay time tval CL =50 pF See Note 5 11 ns tpd Propagation delay time PCLK to shared signal invalid delay time tinv CL = 50 pF, See Note 5 2 ns ten Enable time, high-impedance-to-active delay time from PCLK ton 2 ns tdis Disable time, active-to-high-impedance delay time from PCLK toff 28 ns tsu Setup time before PCLK valid tsu, See Note 6 7 ns th Hold time after PCLK high th, See Note 6 0 ns NOTES: 4. This data sheet uses the following conventions to describe time (t) intervals. The format is: tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time. 5. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR. 6. The setup and hold times for the secondary are identical to those for the primary; however, the times are relative to the secondary PCI close. |
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