Signal descriptions

M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1

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2

Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals

connected to this device.

2.1

Address Inputs (ADQ0-ADQ15 and A16-A22)

ADQ0-ADQ15 and A16-A20 (for the M36L0R7050U1/L1) or A16-A21 (for the

M36L0R7060U1/L1) are common to the Flash memory and PSRAM components.

In the Flash memory, the Address Inputs select the cells in the array to access during Bus

Read operations. During Bus Write operations they control the commands sent to the

Command Interface of the Program/Erase Controller.

In the PSRAM, the Address Inputs A16-A20 (/A21) are used in conjunction with ADQ0 to

ADQ15, to select the cells in the memory array that are accessed during read and write

operations.

2.2

Data Input/Output (ADQ0-ADQ15)

The Data I/O output the data stored at the selected address during a Bus Read operation or

input a command or the data to be programmed during a Bus Write operation.

2.3

Latch Enable (L)

The Latch Enable input is common to the Flash memory and PSRAM components.

For details of how the Latch Enable signal behaves, please refer to the datasheets of the

respective memory components: M69KM048AA or M69KM096AA for the PSRAM and

M58LRxxxGUL for the Flash memory.

2.4

Clock (K)

The Clock input is common to the Flash memory and PSRAM components.

For details of how the Clock signal behaves, please refer to the datasheets of the respective

memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxGUL

for the Flash memory.

2.5

Wait (WAIT)

The Wait output is common to the Flash memory and PSRAM components.

For details of how the WAIT signal behaves, please refer to the datasheets of the respective

memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxGUL

for the Flash memory