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Preliminary Specification
This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27
Integrated Memory Technologies, Inc.
2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696
IMT
80
AA
55
t
WPH
WP
t
WC
Internal Erase Start
2AAA
5555
5555
2AAA
SIX-BYTE COMMAND CODE FOR PAGE ERASE OPERATION
Fig. 5 Page Erase Timing Diagram
5555
55
AA
30
Page Address
ADDRESS
CE
OE
DQ
WE
t
WPH
WP
t
Internal Erase Start
SIX-BYTE COMMAND CODE FOR CHIP ERASE OPERATION
Fig. 6 Chip Erase Timing Diagram
ADDRESS
CE
OE
DQ
WE
t
WHWH2
t
WHWH3
WC
t
t
5555
2AAA
5555
5555
2AAA
5555
AA
55
80
AA
55
10