HD74SSTV16857

Rev.6, Jun. 2001, page 8 of 15

Switching Characteristics

Item

Symbol

V

Unit

Test Condition

Min

Max

Clock frequency

*1

f

clock

—

200

MHz

Setup time

Fast slew rate

*4, 6

t

su

0.75

—

ns

Data before CLK

↑, CLK↓

Slow slew rate

*5, 6

0.9

—

Hold time

Fast slew rate

*4, 6

t

h

0.75

—

ns

Data after CLK

↑, CLK↓

Slow slew rate

*5, 6

0.9

—

Differential inputs

active time

t

act

22

—

ns

Data inputs must be low

after

RESET high.

Differential inputs

inactive time

t

inact

22

—

ns

Data and clock inputs

must be held at valid

levels (not floating) after

RESET low.

Pulse width

t

w

2.5

—

ns

CLK

, CLK “H” or “L”

Output slew

*3

t

SL

1

4

volt/ns

(C

Item

Symbol

V

Unit

FROM

TO

Min

Typ

Max

(Input)

(Output)

Maximum clock frequency

f

max

200

——

MHz

Propagation delay time

*2

t

1.1

—

2.8

ns

CLK,

CLK Q

t

PHL

——

5.0

RESET

Q

Notes: 1. Although the clock is differential, all timing is relative to CLK going high and

CLK going low.

2. This timing relationship is specified into test load (see waveforms – 3, 4) with all of the outputs

switching.

3. Assumes into an equivalent, distributed load to the address net structure defined in the

application information provided in this specification.

4. For data signal input slew rate

≥ 1 V/ns.

5. For data signal input slew rate

≥ 0.5 V/ns and < 1 V/ns.

6. CLK,

CLK signals input slew rates are ≥ 1 V/ns.