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S72NS512PD0KJFGG0 Datasheet(PDF) 9 Page - SPANSION |
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S72NS512PD0KJFGG0 Datasheet(HTML) 9 Page - SPANSION |
9 / 14 page S72NS-P_00_01 September 6, 2006 S72NS-P Based MCPs/PoPs 7 Data Sheet (Adv ance I nf or mation) 5. Ordering Information The order number (Valid Combination) is formed by the following: Notes: 1. Packing Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. 3. Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S72NS 256 P D0 AJ B L G 3 PACKING TYPE 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel FLASH and DDR SPEED G = 66 MHz Flash, 133 MHz DDR DRAM C = 80 MHz Flash, 133 MHz DDR DRAM DDR SUPPLIER G = DRAM Type 1 x16 DDR DRAM L = DRAM Type 5 x16 DDR DRAM PACKAGE MODIFIER G = 133-ball, 11x10mm, FBGA MCP B = 133-ball, 8x8mm, FBGA MCP F = 128-ball, 12x12mm, FBGA PoP PACKAGE AND MATERIAL TYPE AJ = Thin profile Fine-pitch BGA Pb-free LF35 MCP (0.5 mm pitch) KJ = Thin profile Fine-pitch BGA Pb-free PoP (0.65 mm pitch) DDR DRAM AND DATA FLASH DENSITY D0 = 128 Mb DRAM, No Data Flash E0 = 256 Mb DRAM, No Data Flash PROCESS TECHNOLOGY P = 90 nm, MirrorBit TM Technology CODE FLASH DENSITY 512 = 512 Mb 256 = 256 Mb 128 = 128 Mb PRODUCT FAMILY S72NS Multi-Chip Product (MCP) 1.8 V Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus Valid Combinations Product Family Code Flash Density (Mb) Process Technology DRAM Density (Mb) Package Type/ Material DDR Vendor Flash & DDR Speed Packing Type S72NS 128 P D0 AJB, KJF G, L G, C 0, 2, 3 (Note 1) 256 G, C 512 AJG, KJF D0, E0 |
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