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MB89P538P-101 Datasheet(PDF) 4 Page - Fujitsu Component Limited.

Part # MB89P538P-101
Description  8-bit Original Microcontroller CMOS
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Manufacturer  FUJITSU [Fujitsu Component Limited.]
Direct Link  http://edevice.fujitsu.com/fmd/en/index.html
Logo FUJITSU - Fujitsu Component Limited.

MB89P538P-101 Datasheet(HTML) 4 Page - Fujitsu Component Limited.

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MB89530H Series
4
(Continued)
*1 : Depends on operating frequency.
*2 : Using external ROM and MBM27C512.
*3 : tinst represents instruction execution time. This can be selected as 1/4, 1/8, 1/16, 1/64 of the main clock cycle
or 1/2 of the sub clock cycle.
Note : MB89537H/538H have no built-in I2C functions.
To use I2C functions, choose the MB89PV530/MB89P538/537HC/538HC.
Part number
Parameter
MB89537H/537HC
MB89538H/538HC
MB89P538
MB89PV530
Pulse width count
timer
8-bit one-shot timer operation
(supports underflow output, operating clock period : 1, 4, 32 tinst*3, external)
8-bit reload timer operation
(supports square wave output, operating clock period : 1, 4, 32 tinst*3, external)
8-bit pulse width measurement operation
(continuous measurement, H width measurement, L width measurement,
↑ to ↑, ↓ to ↓,
H width measurement and
↑ to↑)
16-bit timer/
counter
16-bit timer operation (operating clock period : 1 tinst*3, external)
16-bit event counter operation (select rising, falling, or both edges)
16-bit
× 1 ch
Serial I/O
8 bit length
Selection of LSB first or MSB first
Transfer clock (2, 8, 32 tinst*3, external)
UART/SIO
CLK synchronous/CLK asynchronous data transfer capability (8, 9 bit with parity bit, or 7,8
bit without parity bit) .
Built-in baud rate generator provides selection of 14 baud rate settings.
UART
CLK synchronous/CLK asynchronous data transfer capability (4, 6, 7, 8 bit with parity bit,
or 5, 7, 8, 9 bit without parity bit) .
Built-in baud rate generator provides selection of 14 baud rate settings.
External clock input, 2-channel 8-bit PWM timer output also available for baud rate
settings.
External interrupt 1
4-channel independent.
Selection of rising, falling, or both edge detection.
Can be used for recovery from standby mode (edge detection also available in stop mode)
External interrupt 2
8-channel independent L level detection.
Can be used for recovery from standby mode.
6-bit PPG,
12-bit PPG
Can generate square wave signals with programmable period.
6-bit
× 1 channel or 12-bit × 2 channels.
I2C bus interface
1-channel , compatible with Intel System Administrator bus version 1.0 and Philips I2C
specifications.
2-line communications (on MB89PV530/P538/537HC/538HC)
A/D converter
10-bit resolution
× 8 channels.
A/D conversion functions (conversion time : 60 tinst*3)
Supports repeated calls from external clock or internal clock.
Standard voltage input provided (AVR)
Standby modes
(power saving modes)
Sleep mode, stop mode, sub clock mode, clock mode.
Process
CMOS


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