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NAND04GW3B2BN1F Datasheet(PDF) 11 Page - STMicroelectronics |
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NAND04GW3B2BN1F Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 58 page NAND04GW3B2B, NAND08GW3B2A Memory array organization 11/58 2 Memory array organization The memory array is made up of NAND structures where 32 cells are connected in series. The memory array is organized in blocks where each block contains 64 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store Error correction Codes, software flags or Bad Block identification. The pages are split into a 2048 Byte main area and a spare area of 64 Bytes. Refer to Figure 4: Memory Array Organization. 2.1 Bad Blocks The NAND Flash 2112 Byte/ 1056 Word Page devices may contain Bad Blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device. The Bad Block Information is written prior to shipping (refer to Section 8.1: Bad Block Management for more details). Table 3 shows the minimum number of valid blocks. The values shown include both the Bad Blocks that are present when the device is shipped and the Bad Blocks that could develop later on. These blocks need to be managed using Bad Blocks Management, Block Replacement or Error Correction Codes (refer to Section 8: Software algorithms). Table 3. Valid Blocks Density of Device Min Max 4 Gbits 4016 4096 8 Gbits(1) 1. The NAND08GW3B2A is composed of two 4 Gbit dice. 8032 8192 |
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