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S71WS512NC0BAIZZ2 Datasheet(PDF) 10 Page - SPANSION |
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S71WS512NC0BAIZZ2 Datasheet(HTML) 10 Page - SPANSION |
10 / 142 page 10 S71WS512NE0BFWZZ_00_A1 June 28, 2004 Advan ce In form ati o n Device Bus Operation Legend: L = Logic 0, H = Logic 1, X = Don’t Care. Note: Default active edge of CLK is the rising edge. Ordering Information Table 1. Device Bus Operations Operation (Asynchronous) - Flash CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE# WE# Addr DQ15- DQ0 UB# LB# RESET# WP# ACC# CLK(See Note) AVD# Read - Address Latched L H H L H L L H Valid Valid X X H H H X H L H H H H Read - Address Steady State L H H L H L L H Valid Valid X X H H H X L H L H H H H Write L H H L H L H L Valid Valid X X H H H X L H L H H H H Standby H H H H H H X X X High-Z X X H H H X X Reset X X X X X X X X X High-Z X X L H H X X Output Disable H H L H H H H H X X X X H H H X X H L H H H H L H H H H H Operation(Synchronous) - Flash CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE# WE# Addr DQ15- DQ0 UB# LB# RESET# WP# ACC# CLK(See Note) AVD# Load Starting Burst Adress L H H L H L X H Valid Data X X H H H H L H H H H Advance Burst Read to Next Address L H H L H L L H X Data X X H H H H H L H H H H Terminate current Burst read cycle H H H H H H X H X High-Z X X H H H X "Terminate current Burst read cycle via RESET#" X X X X X X X H X High-Z X X L H H X X "Terminate current Burst read cycle and start new Burst read cycle" L H H L H L X H Valid Valid X X H H H H L H H H H Operation (Asyncronous) - pSRAM CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE# WE# Addr DQ15- DQ0 UB# LB# RESET# WP# ACC# CLK(See Note) AVD# Read H H L H H H L H Valid Valid L L H H H X H/L H H H H L H Read (Page) H H L H H H L H Valid Valid H/L H/L H H H X H/L H H H H L H Write H H L H H H H L Valid Valid L L H H H X *note H H H H L H Write(Upper Byte) H H L H H H H L Valid Invalid( DQ0-8) L H H H H X *note H H H H L H Valid(DQ 9-15) Write(Lower Byte) H H L H H H H L Valid Valid(DQ 0-8) H L H H H X *note H H H H L H Invalid( DQ9-15) Standby H H H H H H H H X High-Z X X H H H X *note PowerDown H H X L X L X X X High-Z X X H H H X X Output Disable H H L H L H H H X X X X H H H X *note Operation(Syncronous) - pSRAM CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE# WE# Addr DQ15- DQ0 UB# LB# RESET# WP# ACC# CLK(See Note) AVD# Load Starting Burst Adress H H H L H H X H Valid Data X X H H H H H H H H L Advance Burst Read to Next Address H H H L H H L H X Data X X H H H H H H H H H L Terminate current Burst read cycle H H H H H H X H X High-Z X X H H H X "Terminate current Burst read cycle and start new Burst read cycle" H H H L H L X H Valid Valid X X H H H H H H H H H |
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