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NAND04GW3B2BN1E Datasheet(PDF) 8 Page - STMicroelectronics |
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NAND04GW3B2BN1E Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 58 page Summary description NAND04GW3B2B, NAND08GW3B2A 8/58 For information on how to order these options refer to Table 23: Ordering Information Scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to ’1’. See Table 1: Product Description, for all the devices available in the family. Figure 1. Logic Block Diagram Table 1. Product Description Part Number Density Bus Width Page Size Block Size Memor y Array Operating Voltage Timings Package Random access time (max) Sequential access time (min) Page Program (typ) Block Erase (typ) NAND04GW3B2B 4 Gb x8 2048+ 64 Bytes 128K +4K Bytes 64 Pages x 4096 Blocks 2.7 to 3.6V 25µs 30ns 200µs 2ms TSOP48 NAND08GW3B2A 8 Gb x8 64 Pages x 8192 Blocks 25µs 30ns 200µs 2ms TSOP48 (1) 1. The NAND08GW3B2A is composed of two 4 Gbit dice. Address Register/Counter Command Interface Logic P/E/R Controller, High Voltage Generator WP I/O Buffers & Latches E W AI12465 R Y Decoder Page Buffer NAND Flash Memory Array I/O0-I/O7 Command Register CL AL Cache Register RB PRL |
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