Additional Device Features

Dual Integrated SerDes

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Supports backplane and fiber optic applications

Four outputs on each port that directly drive LEDs

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Software-definable function (speed, link, activity) and blinking allow flexible LED

with programmable LED functionality

signaling implementations

Internal phase-locked loop (PLL) for clock generation

•

Lower component count and reduced system cost

can use 25-MHz crystal

JTAG (IEEE 1149.1*) test access port built-in silicon

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Simplified testing using boundary scan

Loop-back capability

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Built-in tests for silicon integrity

Characteristics

Electrical

PCI Express signaling

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3.3 V

Typical targeted power dissipation (in active link state)

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2.8 W @ D0 1000 Mbps

•

730 mW @ D3 100 Mbps (wakeup enabled)

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350 mW @ D3 wakeup disabled

Environmental

Operating temperature

•

1000BASE-T, 0° to 70° C (with thermal management)

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1000BASE-SX/LX (or SerDes backplane), 0° to 70° C

Storage temperature

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– 65° C to 140° C

Physical

Implemented in 90nm complementary metal-oxide

•

Offers lowest geometry to minimize power and size while maintaining quality and reliability

semiconductor (CMOS) process

Package

•

Lead-free

High-Performance Design Features

The Intel 82571EB Gigabit Ethernet Controller for PCI Express is

designed for high performance and low memory latency. The device

is optimized to connect to a system Memory Control Hub (MCH)

using up to four PCI Express lanes. Alternatively, the controller can

connect to an Input/Output (I/O) Control Hub (ICH) that has a PCI

Express interface. Wide internal data paths eliminate performance

bottlenecks by efficiently handling large address and data words.

Combining a parallel and pipelined logic architecture optimized for

Gigabit Ethernet and for independent transmit and receive queues,

the controller efficiently handles packets with minimum latency.

The controller includes advanced interrupt-handling features

and uses efficient ring-buffer descriptor data structures, with

up to 64 packet descriptors cached on chip. A large 48 KByte

per port on-chip packet buffer maintains superior performance.

In addition, using hardware acceleration, the controller offloads

tasks from the host, such as checksum calculations for

transmission control protocol (TCP), user datagram protocol

(UDP), and Internet protocol (IP); header and data splitting;

and TCP segmentation.

The Intel 82571EB Gigabit Ethernet Controller package is a

17 mm x 17 mm, 256-ball grid array.

Order Codes

82571EB

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HL82571EB

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JL82571EB