4S71NS-J

S71NS-J_00_03 October 10, 2006

Data

Sheet

(Adv ance

I nf or mation)

3.

Input/Output Descriptions

Signal

Description

Flash

RAM

R-UB#

pSRAM Upper Byte Control

X

R-LB#

pSRAM Lower Byte Control

X

A21–A16

Address Inputs

XX

ADQ15–ADQ0

Multiplexed Address/Data input/output

X

X

R-CE#

pSRAM Chip Select Input

X

F-CE#

Flash Chip Enable Input. Asynchronous relative to CLK for the Burst mode.

X

OE#

Output Enable Input. Asynchronous relative to CLK for the Burst mode.

X

X

WE#

Write Enable Input.

XX

Device Power Supply (1.7 V–1.95 V).

X

X

Ground

XX

NC

No Connect; not connected internally

X

X

RDY

Ready output; indicates the status of the Burst read. VOL= data invalid. WAIT# pin of pSRAM is

shared with Flash RDY pin for synchronous pSRAM.

XX

CLK

Clock input. The first rising edge of CLK in conjunction with AVD# low latches address input and

activates burst mode operation. After the initial word is output, subsequent rising edges of CLK

increment the internal address counter. CLK should remain low during asynchronous access.

CLK is present on MuxpSRAM Type 3, but not on MuxpSRAM Type 2. As a result, it is a shared

signal on S71NS064JA0, but a flash-only signal on S71NS032J.

XX

AVD#

Address Valid input. Indicates to device that the valid address is present on the address inputs

(address bits A15–A0 are multiplexed, address bits A22–A16 are address only).

be latched on rising edge of CLK.

XX

F-RST#

X

F-ACC

X

R-CRE

Command Register Enable of pSRAM

X

I/O Power Supply (1.7 V to 1.95 V)

X

X

I/O Ground

XX