4

S71WS512N to S71WS512P

2xWS-N_to_WS-P_AN_01E October 3, 2006

A p plication

N ote

When designing software compatible with both devices, users must account for the 8 additional boot sectors

in the S71WS256N, situated logically in the middle of the sector map.

4.2

Bank Architecture

The flash core of the S71WS512N consists of a total of 32 banks, each of which is 2 MB. The flash core of the

S71WS512P contains a total of 16 banks, each of which is 4 MB. This variation may be important to consider

in cases where the simultaneous read/write feature of the devices is being used to ensure that the proper

bank boundaries are accounted for in both cases.

4.3

Chip select

Since the S71WS512N employs two chip selects (one chip select addresses one 32 MB region), it is possible

to configure the address range to be non-contiguous for the two 32 MB regions. However, the S71WS512P is

a monolithic device that can be addressed with only one chip select and has a contiguous address range. If

the S71WS512N is configured with an address gap after the first 32 MB, users must ensure that the software

can also handle a contiguous address range in the S71WS512P.

4.4

Burst Configuration Register

The S71WS512N has two configuration registers (see Table 4.1) of the same type (one in each die) that need

to be configured individually for proper operation of the device. The S71WS512P has two different types of

configuration registers. The S71WS512P has an additional configuration register (see Table 4.2) in which two

bit fields are used. CR1.0 is used to provide additional programmable wait states. In addition, CR 0.6, can be

used to select zero hold mode. Finally, the configuration registers must be programmed in order (CR0 first

and then CR1) or programming will be ignored.

Table 4.1 S29WS256N Configuration Register

CR Bit

Function

Settings

CR 15

Set Device Read Mode

0: Burst Read Mode

1: Asynchronous Read Mode

CR 14

Reserved

0: All Others

1: S29WS256N at 6 or 7 Wait Settings

2nd

3rd

4th

5th

6th

7th

Initial data is valid on the 2nd (3rd, 4th...9th) rising CLK

edge after addresses are latched.

CR 13

Programmable Wait State

00

0

0

1

1

CR 12

0

0

1

1

0

0

CR 11

0

1

0

1

0

1

CR 10

RDY Polarity

0: RDY signal active LOW

1: RDY signal active HIGH (Default)

CR 9

Reserved

1: Default

CR 8

RDY

0: RDY active 1-clock cycle before data

1: RDY active with data

CR 7

Reserved

1: Default

CR 6

Reserved

1: Default

CR 5

Reserved

0: Default

CR 4

Reserved

0: Default

CR 3

Burst Wrap Around

0: No Wrap Around Burst

1: Wrap Around Burst (Default)

Continuous

(Default)

8-Word

Linear Burst

16-Word

Linear Burst

32-Word

Linear Burst

CR 2

Burst Length

00

0

1

CR 1

01

1

0

CR 0

00

1

0