ADV7340 datasheet(41/88 Pages) AD

Part #	ADV7340

Description	Multiformat Video Encoder, Six 12-Bit Noise Shaped Video짰 DACS

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ADV7340/ADV7341

Rev. 0 | Page 41 of 88

Table 27. Register 0x8A to Register 0x98

SR7 to

Bit Number

Reset

SR0

Register

Bit Description

7

6

5

4

3

2

1

0

Register Setting

Value

0

Slave mode.

0x08

SD Slave/Master Mode.

1

Master mode.

0

Mode 0.

0

1

Mode 1.

1

0

Mode 2.

SD Timing Mode.

1

Mode 3.

Reserved.

1

0

No delay.

0

1

2 clock cycles.

1

0

4 clock cycles.

SD Luma Delay.

1

6 clock cycles.

0

−40 IRE.

SD Minimum Luma Value.

1

−7.5 IRE.

0x8A

SD Timing Register 0

SD Timing Reset.

x

A low-high-low transition

resets the internal SD timing

counters.

0

ta = 1 clock cycle.

0x00

0

1

ta = 4 clock cycles.

1

0

ta = 16 clock cycles.

SD HSYNC Width.

1

ta = 128 clock cycles.

0

tb = 0 clock cycles.

0

1

tb = 4 clock cycles.

1

0

tb = 8 clock cycles.

SD HSYNC to VSYNC Delay.

1

tb = 18 clock cycles.

x

0

tc = tb.

SD HSYNC to VSYNC Rising

Edge Delay (Mode 1 Only).

x

1

tc = tb + 32 μs.

0

1 clock cycle.

0

1

4 clock cycles.

1

0

16 clock cycles.

SD VSYNC Width (Mode 2

Only).

1

128 clock cycles.

0

0 clock cycles.

0

1

1 clock cycle.

1

0

2 clock cycles.

0x8B

SD Timing Register 1

(Note: Applicable in

master modes only,

that is, Subaddress

0x8A, Bit 0 = 1)

SD HSYNC to Pixel Data

Adjust.

1

3 clock cycles.

0x8C

SD FSC Register 01

Subcarrier Frequency Bits[7:0].

x

Subcarrier Frequency Bits[7:0].

0x1F

0x8D

SD FSC Register 11

Subcarrier Frequency Bits[15:8].

x

Subcarrier Frequency Bits[15:8].

0x7C

0x8E

SD FSC Register 21

Subcarrier Frequency

Bits[23:16].

x

Subcarrier Frequency

Bits[23:16].

0xF0

0x8F

SD FSC Register 31

Subcarrier Frequency

Bits[31:24].

x

Subcarrier Frequency

Bits[31:24].

0x21

0x90

SD FSC Phase

Subcarrier Phase Bits[9:2].

x

Subcarrier Phase Bits[9:2].

0x00

0x91

SD Closed Captioning

Extended Data on Even Fields.

x

Extended Data Bits[7:0].

0x00

0x92

SD Closed Captioning

Extended Data on Even Fields.

x

Extended Data Bits[15:8].

0x00

0x93

SD Closed Captioning

Data on Odd Fields.

x

Data Bits[7:0].

0x00

0x94

SD Closed Captioning

Data on Odd Fields.

x

Data Bits[15:8].

0x00

0x95

SD Pedestal Register 0

Pedestal on Odd Fields.

17

16

15

14

13

12

11

10

0x00

0x96

SD Pedestal Register 1

Pedestal on Odd Fields.

25

24

23

22

21

20

19

18

0x00

0x97

SD Pedestal Register 2

Pedestal on Even Fields.

17

16

15

14

13

12

11

10

0x00

0x98

SD Pedestal Register 3

Pedestal on Even Fields.

25

24

23

22

21

20

19

18

Setting any of these bits to 1

disables pedestal on the line

number indicated by the bit

settings.

0x00

1 SD subcarrier frequency registers default to NTSC subcarrier frequency values.

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