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S71GS128NB0BAWAK0 Datasheet(PDF) 4 Page - SPANSION |
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S71GS128NB0BAWAK0 Datasheet(HTML) 4 Page - SPANSION |
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4 / 195 page  4 S71GS256/128N_00_A0 December 17, 2004 Advan ce In form ati o n Read-Only Operations–S29GL128N, S29GL256N, S29GL512N .......... 92 Figure 11. Read Operation Timings....................................... 93 Figure 12. Page Read Timings.............................................. 93 Hardware Reset (RESET#) .............................................................................. 94 Figure 13. Reset Timings..................................................... 94 Erase and Program Operations–S29GL128N, S29GL256N, S29GL512N ...................................................................................95 Figure 14. Program Operation Timings .................................. 96 Figure 15. Accelerated Program Timing Diagram .................... 96 Figure 16. Chip/Sector Erase Operation Timings..................... 97 Figure 17. Data# Polling Timings (During Embedded Algorithms) ............................................ 98 Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 99 Figure 19. DQ2 vs. DQ6 ...................................................... 99 Alternate CE# Controlled Erase and Program Operations- S29GL128N, S29GL256N, S29GL512N ........................................................100 Figure 20. Alternate CE# Controlled Write (Erase/ Program) Operation Timings.............................................. 101 Erase And Programming Performance . . . . . . 102 TSOP Pin and BGA Package Capacitance . . . . 102 CellularRAM Type 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 General Description . . . . . . . . . . . . . . . . . . . . . . 103 Figure 21. Functional Block Diagram................................... 104 Table 15. Signal Descriptions .............................................105 Table 16. Bus Operations—Asynchronous Mode ....................106 Table 17. Bus Operations—Burst Mode ................................107 Functional Description . . . . . . . . . . . . . . . . . . . . 107 Power-Up Initialization .................................................................................... 107 Figure 22. Power-Up Initialization Timing............................. 108 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . 108 Asynchronous Mode ........................................................................................108 Figure 23. READ Operation (ADV# LOW)............................. 108 Figure 24. WRITE Operation (ADV# LOW) ........................... 109 Page Mode READ Operation ........................................................................109 Figure 25. Page Mode READ Operation (ADV# LOW)............. 110 Burst Mode Operation .....................................................................................110 Figure 26. Burst Mode READ (4-word burst) ........................ 111 Figure 27. Burst Mode WRITE (4-word burst)....................... 111 Mixed-Mode Operation ...................................................................................112 WAIT Operation ...............................................................................................112 Figure 28. Wired or WAIT Configuration .............................. 112 LB#/UB# Operation .......................................................................................... 113 Figure 29. Refresh Collision During READ Operation.............. 113 Figure 30. Refresh Collision During WRITE Operation ............ 114 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . 114 Standby Mode Operation ................................................................................114 Temperature Compensated Refresh ...........................................................114 Partial Array Refresh ........................................................................................ 115 Deep Power-Down Operation ...................................................................... 115 Configuration Registers . . . . . . . . . . . . . . . . . . . . 115 Access Using CRE .............................................................................................. 115 Figure 31. Configuration Register WRITE, Asynchronous Mode Fol- lowed by READ ................................................................ 116 Figure 32. Configuration Register WRITE, Synchronous Mode Fol- lowed by READ0............................................................... 117 Bus Configuration Register ............................................................................. 117 Table 18. Bus Configuration Register Definition ....................118 Table 19. Sequence and Burst Length .................................119 Burst Length (BCR[2:0]): Default = Continuous Burst ......................119 Burst Wrap (BCR[3]): Default = No Wrap .......................................... 119 Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive Strength ............................................................................................................120 Table 20. Output Impedance ............................................. 120 WAIT Configuration (BCR[8]): Default = WAIT Transitions One Clock Before Data Valid/Invalid ...............................................................120 WAIT Polarity (BCR[10]): Default = WAIT Active HIGH ...............120 Figure 33. WAIT Configuration (BCR[8] = 0) ....................... 120 Figure 34. WAIT Configuration (BCR[8] = 1) ....................... 121 Figure 35. WAIT Configuration During Burst Operation.......... 121 Latency Counter (BCR[13:11]): Default = Three-Clock Latency ......121 Table 21. Variable Latency Configuration Codes ................... 121 Figure 36. Latency Counter (Variable Initial Latency, No Refresh Collision) ........................................................................ 122 Operating Mode (BCR[15]): Default = Asynchronous Operation .122 Refresh Configuration Register .....................................................................122 Table 22. Refresh Configuration Register Mapping ................ 123 Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh ....123 Table 23. 128Mb Address Patterns for PAR (RCR[4] = 1) ....... 123 Table 24. 64Mb Address Patterns for PAR (RCR[4] = 1) ........ 124 Table 25. 32Mb Address Patterns for PAR (RCR[4] = 1) ........ 124 Deep Power-Down (RCR[4]): Default = DPD Disabled ..................124 Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC Op- eration ..............................................................................................................124 Page Mode Operation (RCR[7]): Default = Disabled ........................124 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 125 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 126 Table 26. Electrical Characteristics and Operating Conditions . 126 Table 27. Temperature Compensated Refresh Specifications and Conditions ....................................................................... 127 Table 28. Partial Array Refresh Specifications and Conditions . 127 Table 29. Deep Power-Down Specifications .......................... 127 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 37. AC Input/Output Reference Waveform................. 128 Figure 38. Output Load Circuit........................................... 128 Table 30. Output Load Circuit ............................................ 128 Table 31. Asynchronous READ Cycle Timing Requirements .... 129 Table 32. Burst READ Cycle Timing Requirements ................ 130 Table 33. Asynchronous WRITE Cycle Timing Requirements ... 131 Table 34. Burst WRITE Cycle Timing Requirements ............... 131 Timing Diagrams ................................................................................................132 Figure 39. Initialization Period ........................................... 132 Table 35. Initialization Timing Parameters ........................... 132 Figure 40. Asynchronous READ.......................................... 133 Table 36. Asynchronous READ Timing Parameters ................ 133 Figure 41. Asynchronous READ Using ADV# ........................ 135 Table 37. Asynchronous READ Timing Parameters Using ADV# 135 Figure 42. Page Mode READ .............................................. 137 Table 38. Asynchronous READ Timing Parameters—Page Mode Operation ....................................................................... 137 Figure 43. Single-Access Burst READ Operation—Variable Latency .......................................................................... 139 Table 39. Burst READ Timing Parameters—Single Access, Variable Latency .......................................................................... 139 Figure 44. Four-word Burst READ Operation—Variable Latency 141 Table 40. Burst READ Timing Parameters—4-word Burst ....... 142 Figure 45. Four-word Burst READ Operation (with LB#/UB#). 143 Table 41. Burst READ Timing Parameters—4-word Burst with LB#/ UB# ............................................................................... 144 Figure 46. READ Burst Suspend ......................................... 145 Table 42. Burst READ Timing Parameters—Burst Suspend ..... 145 Figure 47. Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition ................................. 146 Table 43. Burst READ Timing Parameters—BCR[8] = 0 ......... 146 Figure 48. CE#-Controlled Asynchronous WRITE .................. 147 |
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