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FDC37M70X Datasheet(PDF) 75 Page - List of Unclassifed Manufacturers

Part No. FDC37M70X
Description  Enhanced Super I/O Controller with Wake-Up
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Maker  ETC [List of Unclassifed Manufacturers]
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FIFO POLLED MODE OPERATION
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or
3 or all to zero puts the UART in the FIFO
Polled Mode of operation. Since the RCVR and
XMITTER are controlled separately, either one
or both can be in the polled mode of operation.
In this mode, the user's program will check
RCVR and XMITTER status via the LSR. LSR
definitions for the FIFO Polled Mode are as
follows:
-
Bit 0=1 as long as there is one byte in the
RCVR FIFO.
-
Bits 1 to 4 specify which error(s) have
occurred. Character error status is handled
the same way as when in the interrupt
mode, the IIR is not affected since EIR bit
2=0.
-
Bit 5 indicates when the XMIT FIFO is
empty.
-
Bit 6 indicates that both the XMIT FIFO and
shift register are empty.
-
Bit 7 indicates whether there are any errors
in the RCVR FIFO.
There is no trigger level reached or timeout
condition indicated in the FIFO Polled Mode,
however, the RCVR and XMIT FIFOs are still
fully capable of holding characters.
Table 31 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock
for 115.2k ; Using 3.6864MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k
DESIRED
BAUD RATE
DIVISOR USED TO
GENERATE 16X CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
1
HIGH SPEED
BIT
2
50
2304
0.001
X
75
1536
-
X
110
1047
-
X
134.5
857
0.004
X
150
768
-
X
300
384
-
X
600
192
-
X
1200
96
-
X
1800
64
-
X
2000
58
0.005
X
2400
48
-
X
3600
32
-
X
4800
24
-
X
7200
16
-
X
9600
12
-
X
19200
6
-
X
38400
3
0.030
X
57600
2
0.16
X
115200
1
0.16
X
230400
32770
0.16
1
460800
32769
0.16
1
Note
1: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
Note
2: The High Speed bit is located in the Device Configuration Space.




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