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A6402 Datasheet(PDF) 7 Page - Altera Corporation |
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A6402 Datasheet(HTML) 7 Page - Altera Corporation |
7 / 8 page Altera Corporation 63 a6402 Universal Asynchronous Receiver/Transmitter Data Sheet Timing Waveforms Figure 3 shows the timing waveforms for the a6402. Figure 3. a6402 Functional Timing Waveforms Variations & Clarifications The following characteristics distinguish the Altera® a6402 from the Harris HD-6402: s The a6402 does not contain the sfd and rrd inputs, and the outputs are not tri-stated. s In the a6402, the control and transmitter buffer registers are implemented as registers and use trc as a clock source; these registers are implemented as latches in the HD-6402 device. s In the a6402, after mr is deasserted, normal operation can resume on the next rrc or trc rising clock edge. In the HD-6402 device, normal operation does not resume for 18 clock cycles. s Due to the synchronization process in the a6402, tbre is deasserted two clock cycles after the low-to-high transition of ntbrl . In the HD-6402 device, tbre is deasserted immediately after the low-to-high transition of ntbrl. s In the a6402, the tro output is registered to remove glitches. This register uses trc as the clock source. s Once the pe, fe, and oe outputs are asserted, the HD-6402 device has no exit condition other than through asserting mr. Valid Data trc cls[2..1], pi epe, sbs crl Control Register Input Cycle trc tbr[7..0] ntbrl Valid Data Data Input Cycle Start Data LSB Data MSB Parity Stop tro Serial Data Format (7 Bits, 1 Parity Bit, 1 Stop Bit) |
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