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74AUP1G175GF Datasheet(PDF) 4 Page - NXP Semiconductors |
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74AUP1G175GF Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 26 page 74AUP1G175_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx — 27 March 2006 4 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 7. Pinning information 7.1 Pinning 7.2 Pin description Fig 4. Pin configuration SOT363 (SC-88) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 74AUP1G175 5 6MR 2 GND 1 CP 3 D VCC 4Q 001aaa467 74AUP1G175 GND 001aab657 CP D VCC MR Q Transparent top view 2 3 1 5 4 6 74AUP1G175 GND 001aae246 CP D VCC MR Q Transparent top view 2 3 1 5 4 6 Table 4: Pin description Symbol Pin Description CP 1 clock input (LOW-to-HIGH, edge-triggered) GND 2 ground (0 V) D 3 data input Q 4 flip-flop output VCC 5 supply voltage MR 6 master reset input (active LOW) |
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