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QT60486-AS-G Datasheet(PDF) 6 Page - Quantum Research Group |
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QT60486-AS-G Datasheet(HTML) 6 Page - Quantum Research Group |
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6 / 32 page  2-5). Only one key along a particular X line needs to be observed, as each of the keys along that X line will be identical. The chosen dwell time should exceed the observed 95% settling of the X-pulse by 25% or more. In almost all case, Ry should be set equal to Rx, which will ensure that the charge on the Y line is fully captured into the Cs capacitor. 2.9 Key Design Circuits can be constructed out of a variety of materials including flex circuits, FR4, and even inexpensive single-sided CEM-1. The actual internal pattern style is not as important as is the need to achieve regular X and Y widths and spacings of sufficient size to cover the desired graphical key area or a little bit more; ~3mm oversize is acceptable in most cases, since the key’s electric fields drop off near the edges anyway. The overall key size can range from 10mm x 10mm up to 100mm x 100mm but these are not hard limits. The keys can be any shape including round, rectangular, square, etc. The internal pattern can be as simple as a single bar of Y within a solid perimeter of X, or (preferably) interdigitated as shown in Figure 2-6. For better surface moisture suppression, the outer perimeter of X should be as wide as possible, and there should be no ground planes near the keys. The variable ‘T’ in this drawing represents the total thickness of all materials that the keys must penetrate. See Figure 2-6 and page 30 for examples of key layouts. 2.10 PCB Layout, Construction It is best to place the chip near the touch keys on the same PCB so as to reduce X and Y trace lengths, thereby reducing the chances for EMC problems. Long connection traces act as RF antennae. The Y (receive) lines are much more susceptible to noise pickup than the X (drive) lines. Even more importantly, all signal related discrete parts (R’s and C’s) should be very close to the body of the chip. Wiring between the chip and the various R’s and C’s should be as short and direct as possible to suppress noise pickup. Ground planes and traces should NOT be used around the keys and the Y lines from the keys. Ground areas, traces, and other adjacent signal conductors that act as AC ground (such as Vdd and LED drive lines etc) will absorb the received key signals and reduce signal-to-noise ratio (SNR) and thus will be counterproductive. Ground planes around keys will also make water film effects worse. Ground planes, if used, should be placed under or around the QT chip itself and the associated R’s and C’s in the circuit, under or around the power supply, and back to a connector, but nowhere else. See page 30 for an example of a 1-sided PCB layout. 2.10.1 LED Traces and Other Switching Signals Digital switching signals near the Y lines will induce transients into the acquired signals, deteriorating the SNR perfomance of the device. Such signals should be routed away from the Y lines, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). LED terminals which are multiplexed or switched into a floating state and which are within or physically very near a key structure (even if on another nearby PCB) should be bypassed to either Vss or Vdd with at least a 10nF capacitor of any type, to suppress capacitive coupling effects which can induce false signal shifts. Led terminals which are constantly connected to Vss or Vdd do not need further bypassing. 2.10.2 PCB Cleanliness All capacitive sensors should be treated as highly sensitive circuits which can be influenced by stray conductive leakage paths. QT devices have a basic resolution in the femtofarad range; in this region, there is no such thing as ‘no clean flux’. Flux absorbs moisture and becomes conductive between solder joints, causing signal drift and resultant false detections or transient losses of sensitivity or instability. Conformal coatings will trap in existing amounts of moisture which will then become highly temperature sensitive. The designer should specify ultrasonic cleaning as part of the manufacturing process, and in cases where a high level of humidity is anticipated, the use of conformal coatings after cleaning to keep out moisture. 2.11 Power Supply Considerations As these devices use the power supply itself as an analog reference, the power should be very clean and come from a separate regulator. A standard inexpensive LDO type regulator should be used that is not also used to power other loads such as LEDs, relays, or other high current devices. Load shifts on the output of the LDO can cause Vdd to fluctuate enough to cause false detection or sensitivity shifts. Ceramic 0.1uF bypass capacitors should be placed very close and routed with short traces to all power pins of the IC. There should be at least 3 such capacitors around the part. 2.12 Startup / Calibration Times The devices require initialization times as follows: 1. From very first powerup to ability to communicate: 2,083ms (one time event to initialize all of eeprom, or to recover eeprom copy from FLASH in the event of eeprom corruption) 2. From powerup to ability to communicate: 2,100 ms in the event the part is being forced to restore the factory defaults. 3. From powerup to ability to communicate: 36 ms in the event the setups have been changed and the part needs to backup the EEPROM to flash. 4. Normal cold start to ability to communicate: 3ms (Normal initialization from any reset) 5. Calibration time per key vs. burst spacings for 32 and 48 enabled keys (Table below): lQ 6 QT60486-AS R8.01/0105 |
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