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IDT723672L12PF Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT723672L12PF Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 29 page 8 COMMERCIALTEMPERATURERANGE IDT723652/723662/723672 CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 Commercial IDT723652L12 IDT723652L15 IDT723662L12 IDT723662L15 IDT723672L12 IDT723672L15 Symbol Parameter Min. Max. Min. Max. Unit fS Clock Frequency, CLKA or CLKB — 83 — 66.7 MHz tCLK Clock Cycle Time, CLKA or CLKB 12 — 15 — ns tCLKH Pulse Duration, CLKA or CLKB HIGH 5 — 6 — ns tCLKL Pulse Duration, CLKA and CLKB LOW 5 — 6 — ns tDS Setup Time, A0-A35 before CLKA ↑ and B0-B35 before CLKB↑ 3— 4— ns tENS1 Setup Time, CSA and W/RA, before CLKA ↑; CSB, and W/RB before CLKB↑ 4 — 4.5 — ns tENS2 Setup Time, ENA and MBA, before CLKA ↑; ENB, and MBB before CLKB↑ 3 — 4.5 — ns tRSTS Setup Time, RST1 or RST2 LOW before CLKA ↑ or CLKB↑(1) 5— 5— ns tFSS Setup Time, FS0 and FS1 before RST1 and RST2 HIGH 7.5 — 7.5 — ns tFWS Setup Time, FWFT before CLKA ↑ 0— 0— ns tDH Hold Time, A0-A35 after CLKA ↑ and B0-B35 after CLKB↑ 0.5 — 1 — ns tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA ↑; CSB, W/RB, ENB, and 0.5 — 1 — ns MBB after CLKB ↑ tRSTH Hold Time, RST1 or RST2 LOW after CLKA ↑ or CLKB↑(1) 4— 4— ns tFSH Hold Time, FS0 and FS1 after RST1 and RST2 HIGH 2 — 2 — ns tSKEW1(2) Skew Time, between CLKA ↑ and CLKB↑ for EFA/ORA, EFB/ORB, FFA/IRA, 7.5 — 7.5 — ns and FFB/IRB tSKEW2(2,3) Skew Time, between CLKA ↑ and CLKB↑ for AEA, AEB, AFA, and AFB 12 — 12 — ns NOTES: 1. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. 3. Design simulated, not tested. 4. Industrial temperature range is available by special order. TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (Commercial: VCC = 5V ± 10%, TA = 0 °C to +70°C) |
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