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LX8384A-XXCP Datasheet(PDF) 2 Page - Microsemi Corporation |
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LX8384A-XXCP Datasheet(HTML) 2 Page - Microsemi Corporation |
2 / 11 page Microsemi Linfinity Microelectronics Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 Copyright © 2000 Rev. 2.1d, 2001-03-15 LX8384x-xx 5A Low Dropout Positive Regulators PRODUCTION A M I CROS E M I COM P A N Y Power Dissipation....................................................................................Internally Limited Input Voltage .................................................................................................................10V Input to Output Voltage Differential..............................................................................10V Operating Junction Temperature Plastic (DT, DD, P Packages) ................................................................................ 150°C Storage Temperature Range .......................................................................-65°C to 150 °C Lead Temperature (Soldering, 10 Seconds)............................................................... 300°C Note 1: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal. DD Plastic TO-263 3-Pin THERMAL RESISTANCE -JUNCTION TO AMBIENT, θ JA 60 °C/W THERMAL RESISTANCE -JUNCTION TO TAB, θ JT 2.7°C/W P Plastic TO-220 3-Pin THERMAL RESISTANCE -JUNCTION TO AMBIENT, θ JA 60 °C/W THERMAL RESISTANCE -JUNCTION TO TAB, θ JT 2.7°C/W DT Plastic TO-252 3-Pin THERMAL RESISTANCE -JUNCTION TO AMBIENT, θ JA 60 °C/W THERMAL RESISTANCE -JUNCTION TO TAB, θ JT 2.7°C/W Junction Temperature Calculation: TJ = TA + (PD x θJT). The θ JA & θJT numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. 1 V IN AD J / G ND* V OU T 2 3 T AB is V OU T DD PACKAGE (3-PIN) (Top View) V IN V OU T AD J/ GN D* TA B is V OU T 3 2 1 DT PACKAGE (3-PIN) (Top View) TA B is V OU T AD J / GN D* V OU T V IN 1 2 3 P PACKAGE (3-PIN) (Top View) *Pin 1 is GND for fixed voltage versions Therm al Lim it C ircuit Bias Circuit B andgap Circuit Control Circuit Output Circuit SO A P rotection Circuit Current Lim it C ircuit V IN ADJ or G ND* V OUT *Pin 1 is GND for fixed voltage versions |
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