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ADSP-21266SKBCZ-2B Datasheet(PDF) 10 Page - Analog Devices |
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ADSP-21266SKBCZ-2B Datasheet(HTML) 10 Page - Analog Devices |
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10 / 44 page  Rev. B | Page 10 of 44 | May 2005 ADSP-21266 The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the mem- ory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, pre- emptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the gen- eration of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK. VisualDSP++ Component Software Engineering (VCSE) is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applica- tions. It also is used for downloading components from the Web, dropping them into the application, and publishing com- ponent archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utiliza- tion in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with a drag of the mouse, and examine run-time stack and heap usage. The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphi- cal and textual environments. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hard- ware tools include SHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. EVALUATION KIT Analog Devices offers a range of EZ-KIT Lite ®† evaluation plat- forms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the Visu- alDSP++ evaluation suite to emulate the on-board processor in- circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in- circuit programming of the on-board flash device to store user- specific boot code, enabling the board to run as a standalone unit, without being connected to the PC. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any cus- tom-defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonin- trusive emulation. DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG inter- face—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal fea- tures of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on sys- tem timing. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21266 architecture and functionality. For detailed information on the ADSP-2126x family core architecture and instruction set, refer to the ADSP-2126x DSP Core Manual and the ADSP-21160 SHARC DSP Instruction Set Reference. † EZ-KIT Lite is a registered trademark of Analog Devices, Inc. |
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