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IDT70T9159L7BF Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT70T9159L7BF Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 16 page 6.42 IDT70T9169/59L High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 5 Preliminary Recommended Operating Temperature and Supply Voltage Recommended DC Operating Conditions Absolute Maximum Ratings(1) Capacitance(1) (TA = +25°C, f = 1.0MHz) Grade Ambient Temperature (1) GND VDD Commercial 0OC to +70OC0V 2.5V + 100mV Industrial -40OC to +85OC0V 2.5V + 100mV 5654 tbl 04 Sym bol Parameter Min. Typ. Max. Unit V DD Sup p ly Vo ltag e 2.4 2.5 2.6 V V SS Ground 0 0 0 V V IH Input High Vo ltag e 1.7 ____ V DD+0.3V(2) V V IL Inp ut Lo w Vo ltag e -0.3(1) ____ 0.7 V 5654 tbl 05 Symbol Parameter Conditions (2) Max. Unit CIN Input Capacitance VIN = 3dV 9 pF COUT (3) Output Capacitance VOUT = 3dV 10 pF 5654 tbl 07 Symbol Rating Commercial & Industrial Unit VTERM(2) Terminal Voltage with Respect to GND -0.5 to +3.6 V TBIAS Temperature Under Bias -55 to +125 oC TSTG Storage Temperature -65 to +150 oC IOUT DC Output Current 50 mA 5654 tbl 06 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0 and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other signals including CE0 and CE1. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1. Truth Table IIAddress Counter Control(1,2) External Address Previous Internal Address Internal Address Used CLK ADS CNTEN CNTRST I/O(3) MODE An X An ↑ L(4) XH DI/O (n) External Address Used XAn An + 1 ↑ H L(5) HDI/O(n+1) Counter Enabled—Internal Address generation X An + 1 An + 1 ↑ HH H DI/O(n+1) External Addre ss Blocked—Counter disab led (An + 1 reused) XX A0 ↑ XX L(4) DI/O(0) Counter Reset to Address 0 5654 tbl 03 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VDD +0.3V. NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V. |
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