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IDT23S08T-2DC Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT23S08T-2DC Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 6 page 3 COMMERCIALTEMPERATURERANGE IDT23S08T 2.5V ZERO DELAY CLOCK MULTIPLIER S2 S1 CLK A CLK B Output Source PLL Shut Down L L Tri-State Tri-State PLL Y L H Driven Tri-State PLL N H L Driven Driven REF Y H H Driven Driven PLL N FUNCTION TABLE(1) SELECT INPUT DECODING NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level SPREAD SPECTRUM COMPATIBLE Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization. Device FeedbackFrom Bank A Frequency Bank B Frequency IDT23S08T-1 Bank A or Bank B Reference Reference IDT23S08T-2(1) Bank A Reference Reference/2 IDT23S08T-2(1) Bank B 2 x Reference Reference IDT23S08T-3(1) Bank A 2 x Reference Reference or Reference(2) IDT23S08T-3(1) Bank B 4 x Reference 2 x Reference IDT23S08T-4(1) Bank A or Bank B 2 x Reference 2 x Reference IDT23S08T-5(1) Bank A or Bank B Reference/2 Reference/2 NOTES: 1. Contact factory for availability. 2. Output phase is indeterminant (0° or 180° from input clock). AVAILABLE OPTIONS FOR IDT23S08T ZERO DELAY AND SKEW CONTROL To close the feedback loop of the IDT23S08T, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are loaded equally, for zero output-output skew. NOTE: 1. Applies to both REF and FBK. Symbol Parameter Test Conditions Min. Max. Unit VDD SupplyVoltage 2.3 2.7 V TA OperatingTemperature(AmbientTemperature) 0 70 °C CL Load Capacitance from 10MHz to 133MHz — 15 pF CIN InputCapacitance(1) —7 pF OPERATING CONDITIONS |
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