VRS51x570/580
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Upper 128 bytes (80h to FFh, Bank 2 & Bank 3)
The upper 128 bytes of the data memory ranging from
80h to FFh can be accessed using indirect addressing
or by using the bank mapping in direct addressing
mode.
FIGURE 5: VRS51X570 / VRS51X580 INTERNAL LOWER 256 BYTES RAM STRUCTURE
Registers Bank 0
R7
-
R0
Registers Bank 1
R7
-
R0
Registers Bank 2
R7
-
R0
Registers Bank 3
R7
-
R0
80 Bytes of
General Purpose RAM
00h
08h
10h
18h
20h
07
06
05
04
03
02
01
00
0F
0E
0D
0C
0B
0A
09
08
77
76
75
74
73
72
71
70
7F
7E
7D
7C
7B
7A
79
78
30h
128 Bytes of
Indirect Access RAM
(SP, R0,R1)
80h
7Fh
FFh
2Fh
SFR Area
Direct or Bit Access
Only
FFh
85
84
83
82
81
80
P0
SP
DPL
DPH
Expanded RAM Access Using the MOVX @DPTR
Instruction (0000-02FF, Bank4-Bank15)
The 768 bytes of the expanded RAM data memory
occupy addresses 0000h to 02FFh. This block can be
accessed using external direct addressing (i.e. using
the MOVX instruction) or by using bank mapping direct
addressing.
Note that when accessing addresses above 02FFh, the
VRS51x570/VRS51x580 devices will access off-chip
memory in the external memory space using the
external memory control signals.
Expanded RAM Control Register
The 768 bytes of expanded RAM can also be accessed
using the MOVX @Rn instruction (where n = 0,1). The
scope of this instruction is limited to a data range of
256 bytes and therefore the internal RAM Control
Register RCON should be used to select which 256
byte block will be accesseded by the MOVX @Rn
instruction (configuring by bits RAM0 and RAM1).
The default setting of the RAM1 and RAM0 bits is 00
(page 0). Each page has 256 bytes.
TABLE 8: INTERNAL RAM CONTROL REGISTER (RCON) - SFR 85H
7
6
5
4
3
2
1
0
Unused
RAM1
RAM0
Bit
Mnemonic
Description
7
Unused
-
6
Unused
-
5
Unused
-
4
Unused
-
3
Unused
-
2
Unused
-
1
RAM1
0
RAM0
These two bits are used with Rn of instruction
MOVX @Rn, n=1,0 for mapping (see section
on extended 768 bytes)
RAM1, RAM0
Mapped area
00
000h-0FFh
01
100h-1FFh
10
200h-2FFh
11
XY00h-XYFF*
*Externally generated
Example:
Suppose that RAM1, RAM0 are set to 0 and 1 respectively
and Rn has a value of 45h.
Performing MOVX @Rn, A, (where n is 0 or 1) allows the
user to transfer the value of A to the expanded RAM at
address 145h (page 1).
Note that when both RAM1, RAM0 are set to 1, the
value of P2 defines the upper byte and Rn defines the
lower byte of the external address.
In this case the
device will access off-chip memory in the external
memory space using the external memory control
signals, Off chip peripherals can therefore be mapped
into the “P2value”00h to “P2value”FFh address range.
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