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IDT72T51553 Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT72T51553 Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 57 page  8 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Description Pin No. FSTR PAFn Flag Bus LVTTL If direct operation of the PAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK (R4) Strobe INPUT and the WRADD bus to select a quadrant of queues to be placed on to the PAFnbusoutputs.Aquadrant addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If Polled operations has been selected, FSTR should be tied inactive, LOW. FSYNC PAFn Bus Sync LVTTL FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAFnbus (R3) OUTPUT during Polled operation of the PAFn bus. During Polled operation each quadrant of queue status flags is loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads quadrant 1 on to PAFn,thesecondWCLKrisingedgeloadsquadrant2andsoon.ThefifthWCLKrising edge will again load quadrant 1. During the WCLK cycle that quadrant 1 of a selected device is placed on to the PAFn bus, the FSYNC output will be HIGH. For all other quadrants of that device, the FSYNC output will be LOW. FXI PAFn Bus LVTTL The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn (T2) Expansion In INPUT bus operation has been selected. FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI receives a token from the previous device in a chain. In single device mode the FXI input must be tied LOW if the PAFnbusisoperatedindirectmode.IfthePAFnbusisoperatedinpolledmodetheFXIinput must be connected to the FXO output of the same device. In expansion mode the FXI of the first device should be tied LOW, when direct mode is selected. FXO PAFn Bus LVTTL FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled (T3) Expansion Out OUTPUT PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This pin pulses when device N has placed its final (4th) quadrant on to the PAFn bus with respect to WCLK. This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising edge the first quadrant of device N+1 will be loaded on to the PAFnbus.Thiscontinuesthroughthechain andFXOofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputofeachdevice in the chain provides synchronization to the user of this looping event. ID[2:0](1) Device ID Pins LVTTL Forthe32Qmulti-queuedevicetheWRADDandRDADDaddressbussesare8bitswide.Whenaqueue (ID2-C9 INPUT selection takes place the 3 MSb’s of this 8 bit address bus are used to address the specific device (the ID1-A10 5 LSb’s are used to address the queue within that device). During write/read operations the 3 MSb’s ID0-B10) of the address are compared to the device ID pins. The first device in a chain of multi-queue’s (connected in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which is‘111’,howevertheIDdoesnothavetomatchthedeviceorder.Insingledevicemodethesepinsshould be setup as ‘000’ and the 3 MSb’s of the WRADD and RDADD address busses should be tied LOW. The ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’. IOSEL IO Select LVTTL This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are (C8) INPUT required then IOSEL should be tied LOW. If LVTTL I/O are required then it should be tied HIGH. IW(1) InputWidth LVTTL IW selects the bus width for the data input bus. If IW is LOW during a Master Reset then the bus width (L15) INPUT is x18, if HIGH then it is x9. MAST(1) Master Device LVTTL ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe (K15) INPUT MasterdeviceoraSlave.IfthispinisHIGH,thedeviceisthemasterifitisLOWthenitisaSlave.Themaster deviceisthefirsttotakecontrolofalloutputsafteramasterreset,allslavedevicesgotoHigh-Impedance, preventing bus contention. If a multi-queue device is being used in single device mode, this pin must be set HIGH. MRS Master Reset LVTTL Amasterresetisperformedbytaking MRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired (T9) INPUT aftermasterreset. NULL-Q Null Queue HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD (J2) Select INPUT address bus to address the Null-Q. OE OutputEnable LVTTL TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontrolofthemulti-queue (M14) INPUT data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will be in a Low Impedance condition if the OEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbe in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be |
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