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VMX51C900
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DIP-40 Pin Descriptions
TABLE 3: VMX51C900 PIN DESCRIPTIONS FOR DIP40 PACKAGE
DIP -
40
Name
I/O
Function
T2
I
Timer 2 Clock Out
1
P1.0
I/O
Bit 0 of Port 1
T2EX
I
Timer 2 Control
2
P1.1
I/O
Bit 1 of Port 1
P1.2
I/O
Bit 2 of Port 1
3
PWMA
O
PWM Channel A
4
P1.3
I/O
Bit 3 of Port 1
5
P1.4
I/O
Bit 4 of Port 1
PWMB
O
PWM Channel B
6
P1.5
I/O
Bit 5 of Port 1
7
P1.6
I/O
Bit 6 of Port 1
8
P1.7
I/O
Bit 7 of Port 1
9
RES
I
Reset
RXD
I
Receive Data
10
P3.0
I/O
Bit 0 of Port 3
TXD
O
Transmit Data &
11
P3.1
I/O
Bit 1 of Port 3
#INT0
I
External Interrupt 0
12
P3.2
I/O
Bit 2 of Port 3
#INT1
I
External Interrupt 1
13
P3.3
I/O
Bit 3 of Port 3
ADCIN0
Ain
ADC input 0
T0
I
Timer 0
14
P3.4
I/O
Bit 4 of Port 3
ADCIN1
Ain
ADC input 1
T1
I
Timer 1 & 3
15
P3.5
I/O
Bit 5 of Port
ADCIN2
Ain
ADC input 2
#WR
O
Ext. Memory Write
16
P3.6
I/O
Bit 6 of Port 3
ADCIN3
Ain
ADC input 3
#RD
O
Ext. Memory Read
17
P3.7
I/O
Bit 7 of Port 3
18
XTAL2
O
Oscillator/Crystal Output
19
XTAL1
I
Oscillator/Crystal In
20
VSS
-
Ground
LCDCOM0
-
LCD Driver Common 0
P2.0
I/O
Bit 0 of Port 2
21
A8
O
Bit 8 of Ext. Memory Address
LCDCOM1
-
LCD Driver Common 1
P2.1
I/O
Bit 1 of Port 2
22
A9
O
Bit 9 of Ext. Memory Address
LCDCOM2
-
LCD Driver Common 2
P2.2
I/O
Bit 2 of Port 2
23
A10
O
Bit 10 of Ext. Memory Address
LCDCOM3
-
LCD Driver Common 3
P2.3
I/O
Bit 3 of Port 2 &
24
A11
O
Bit 11 of Ext. Memory Address
LCDSEG0
-
LCD Segment 0
P2.4
I/O
Bit 4 of Port 2
25
A12
O
Bit 12 of Ext. Memory Address
LCDSEG1
-
LCD Segment 1
P2.5
I/O
Bit 5 of Port 2
26
A13
O
Bit 13 of External Memory Address
LCDSEG2
-
LCD Segment 2
P2.6
I/O
Bit 6 of Port 2
27
A14
O
Bit 14 of External Memory Address
PLCC
- 44
Name
I/O
Function
LCDSEG3
-
LCD Segment 3
P2.7
I/O
Bit 7 of Port 2
28
A15
O
Bit 15 of External Memory Address
LCDSEG4
-
LCD Segment 4
29
#PSEN
O
Program Store Enable
LCDSEG5
-
LCD Segment 5
30
ALE
O
Address Latch Enable
31
#EA
I
External Access
LCDSEG6
-
LCD Segment 6
P0.7
I/O
Bit 7 Of Port 0
32
AD7
I/O
Data/Address Bit 7 of Ext. Memory
LCDSEG7
-
LCD Segment 7
P0.6
I/O
Bit 6 of Port 0
33
AD6
I/O
Data/Address Bit 6 of Ext. Memory
LCDSEG8
-
LCD Segment 8
P0.5
I/O
Bit 5 of Port 0
34
AD5
I/O
Data/Address Bit 5 of Ext. Memory
LCDSEG9
-
LCD Segment 9
P0.4
I/O
Bit 4 of Port 0
35
AD4
I/O
Data/Address Bit 4 of Ext. Memory
LCDSEG10
-
LCD Segment 10
P0.3
I/O
Bit 3 Of Port 0
36
AD3
I/O
Data/Address Bit 3 of Ext. Memory
LCDSEG11
-
LCD Segment 11
P0.2
I/O
Bit 2 of Port 0
37
AD2
I/O
Data/Address Bit 2 of Ext. Memory
LCDSEG12
-
LCD Segment 12
P0. 1
I/O
Bit 1 of Port 0 & Data
38
AD1
I/O
Address Bit 1 of Ext. Memory
LCDSEG13
-
LCD Segment 13
P0.0
I/O
Bit 0 Of Port 0 & Data
39
AD0
I/O
Address Bit 0 of Ext. Memory
40
VDD
-
5V supply
T2 / P1.0
T2EX / P1.1
PWMA / P1.2
P1.3
P1.4
PWMB / P1.5
P1.6
P1.7
RESET
RXD / P3.0
TXD / P3.1
#INT0 / P3.2
#INT1 / P3.3
ADCIN0 / T0 / P3.4
ADCIN1 / T1 / P3.5
ADCIN2 / #WR / P3.6
ADCIN3 / #RD / P3.7
XTAL2
XTAL1
VSS
VMX51C900
DIP-40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
P0.0 / AD0 / LCDSEG13
P0.1 / AD1 / LCDSEG12
P0.2 / AD2 / LCDSEG11
P0.3 / AD3 / LCDSEG10
P0.4 / AD4 / LCDSEG9
P0.5 / AD5 / LCDSEG8
P0.6 / AD6 / LCDSEG7
P0.7 / AD7 / LCDSEG6
#EA / VPP
ALE / LCDSEG5
PSEN / LCDSEG4
P2.7 / A15 / LCDSEG3
P2.6 / A14 / LCDSEG2
P2.5 / A13 / LCDSEG1
P2.4 / A12 / LCDSEG0
P2.3 / A11 / LCDCOM3
P2.2 / A10 / LCDCOM2
P2.1 / A9 / LCDCOM1
P2.0 / A8 / LCDCOM0