VMX51C900
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page 6 of 55
Instruction Set
The following tables describe the instruction set of the
VMX51C900. The instructions are function and binary code
compatible with industry standard 8051s.
TABLE 4: LEGEND FOR INSTRUCTION SET TABLE
Symbol
Function
A
Accumulator
Rn
Register R0-R7
Direct
Internal register address
@Ri
Internal register pointed to by R0 or R1 (except MOVX)
rel
Two's complement offset byte
bit
Direct bit address
#data
8-bit constant
#data 16
16-bit constant
addr 16
16-bit destination address
addr 11
11-bit destination address
TABLE 5: VRS570/VRS580 INSTRUCTION SET
Mnemonic
Description
Size
(bytes)
Instr.
Cycles
Op-
Code
Arithmetic instructions
ADD A, Rn
Add register to A
1
1
28h-2Fh
ADD A, direct
Add direct byte to A
2
1
25h
ADD A, @Ri
Add data memory to A
1
1
26h,27h
ADD A, #data
Add immediate to A
2
1
24h
ADDC A, Rn
Add register to A with carry
1
1
38h-3Fh
ADDC A, direct
Add direct byte to A with carry
2
1
35h
ADDC A, @Ri
Add data memory to A with carry
1
1
36h,37h
ADDC A, #data
Add immediate to A with carry
2
1
34h
SUBB A, Rn
Subtract register from A with borrow
1
1
98h-9Fh
SUBB A, direct
Subtract direct byte from A with borrow
2
1
95h
SUBB A, @Ri
Subtract data mem from A with borrow
1
1
96h-97h
SUBB A, #data
Subtract immediate from A with borrow
2
1
94h
INC A
Increment A
1
1
04h
INC Rn
Increment register
1
1
08h-0Fh
INC direct
Increment direct byte
2
1
05h
INC @Ri
Increment data memory
1
1
06h, 07h
DEC A
Decrement A
1
1
14h
DEC Rn
Decrement register
1
1
18h-1Fh
DEC direct
Decrement direct byte
2
1
15h
DEC @Ri
Decrement data memory
1
1
16h,17h
INC DPTR
Increment data pointer
1
2
A3h
MUL AB
Multiply A by B
1
4
A4h
DIV AB
Divide A by B
1
4
84h
DA A
Decimal adjust A
1
1
D4h
Logical Instructions
ANL A, Rn
AND register to A
1
1
58h-5Fh
ANL A, direct
AND direct byte to A
2
1
55h
ANL A, @Ri
AND data memory to A
1
1
56-57h
ANL A, #data
AND immediate to A
2
1
54h
ANL direct, A
AND A to direct byte
2
1
52h
ANL direct, #data
AND immediate data to direct byte
3
2
53h
ORL A, Rn
OR register to A
1
1
48h-4Fh
ORL A, direct
OR direct byte to A
2
1
45h
ORL A, @Ri
OR data memory to A
1
1
46h,47h
ORL A, #data
OR immediate to A
2
1
44h
ORL direct, A
OR A to direct byte
2
1
42h
ORL direct, #data
OR immediate data to direct byte
3
2
43h
XRL A, Rn
Exclusive-OR register to A
1
1
68h-6Fh
XRL A, direct
Exclusive-OR direct byte to A
2
1
65h
XRL A, @Ri
Exclusive-OR data memory to A
1
1
66h,67h
XRL A, #data
Exclusive-OR immediate to A
2
1
64h
XRL direct, A
Exclusive-OR A to direct byte
2
1
62h
XRL direct, #data
Exclusive-OR immediate to direct byte
3
2
63h
CLR A
Clear A
1
1
E4h
CPL A
Compliment A
1
1
F4h
SWAP A
Swap nibbles of A
1
1
C4h
RL A
Rotate A left
1
1
23h
RLC A
Rotate A left through carry
1
1
33h
RR A
Rotate A right
1
1
03h
RRC A
Rotate A right through carry
1
1
13h
Mnemonic
Description
Size
(bytes)
Instr.
Cycles
Op
Code
Boolean Instruction
CLR C
Clear Carry bit
1
1
C3h
CLR bit
Clear bit
2
1
C2h
SETB C
Set Carry bit to 1
1
1
D3h
SETB bit
Set bit to 1
2
1
D2h
CPL C
Complement Carry bit
1
1
B3h
CPL bit
Complement bit
2
1
B2h
ANL C,bit
Logical AND between Carry and bit
2
2
82h
ANL C,#bit
Logical AND between Carry and not bit
2
2
A0h,B0h
ORL C,bit
Logical ORL between Carry and bit
2
2
72h
ORL C,#bit
Logical ORL between Carry and not bit
2
2
A0h
MOV C,bit
Copy bit value into Carry
2
1
A2h
MOV bit,C
Copy Carry value into Bit
2
2
92h
Data Transfer Instructions
MOV A, Rn
Move register to A
1
1
E8h-Efh
MOV A, direct
Move direct byte to A
2
1
E5h
MOV A, @Ri
Move data memory to A
1
1
E6h,E7h
MOV A, #data
Move immediate to A
2
1
74h
MOV Rn, A
Move A to register
1
1
F8h-FFh
MOV Rn, direct
Move direct byte to register
2
2
A8h-AFh
MOV Rn, #data
Move immediate to register
2
1
78h-7Fh
MOV direct, A
Move A to direct byte
2
1
F5h
MOV direct, Rn
Move register to direct byte
2
2
88h-8Fh
MOV direct, direct
Move direct byte to direct byte
3
2
85h
MOV direct, @Ri
Move data memory to direct byte
2
2
86h,87h
MOV direct, #data
Move immediate to direct byte
3
2
75h
MOV @Ri, A
Move A to data memory
1
1
F6h,F7h
MOV @Ri, direct
Move direct byte to data memory
2
2
A6h,A7h
MOV @Ri, #data
Move immediate to data memory
2
1
76h-77h
MOV DPTR, #data
Move immediate to data pointer
3
2
90h
MOVC A, @A+DPTR
Move code byte relative DPTR to A
1
2
93h
MOVC A, @A+PC
Move code byte relative PC to A
1
2
83h
MOVX A, @Ri
Move external data (A8) to A
1
2
E2h,E3h
MOVX A, @DPTR
Move external data (A16) to A
1
2
E0h
MOVX @Ri, A
Move A to external data (A8)
1
2
F2h,F3h
MOVX @DPTR, A
Move A to external data (A16)
1
2
F0h
PUSH direct
Push direct byte onto stack
2
2
C0h
POP direct
Pop direct byte from stack
2
2
D0h
XCH A, Rn
Exchange A and register
1
1
C8h-CFh
XCH A, direct
Exchange A and direct byte
2
1
C5h
XCH A, @Ri
Exchange A and data memory
1
1
C6h,C7h
XCHD A, @Ri
Exchange A and data memory nibble
1
1
D6h,D7h
Branching Instructions
ACALL addr 11
Absolute call to subroutine
2
2
11h,31h,
51h,71h,
91h,B1h,
D1h,F1h
LCALL addr 16
Long call to subroutine
3
2
12h
RET
Return from subroutine
1
2
22h
RETI
Return from interrupt
1
2
32h
AJMP addr 11
Absolute jump unconditional
2
2
01h,21h,
41h,61h,
81h,A1h,
C1h,E1h
LJMP addr 16
Long jump unconditional
3
2
02h
SJMP rel
Short jump (relative address)
2
2
80h
JC rel
Jump on carry = 1
2
2
40h
JNC rel
Jump on carry = 0
2
2
50h
JB bit, rel
Jump on direct bit = 1
3
2
20h
JNB bit, rel
Jump on direct bit = 0
3
2
30h
JBC bit,rel
Jump on direct bit = 1 and clear
3
2
10h
JMP @A+DPTR
Jump indirect relative DPTR
1
2
73h
JZ rel
Jump on accumulator = 0
2
2
60h
JNZ rel
Jump on accumulator 1= 0
2
2
70h
CJNE A, direct, rel
Compare A, direct JNE relative
3
2
B5h
CJNE A, #d, rel
Compare A, immediate JNE relative
3
2
B4h
CJNE Rn, #d, rel
Compare reg, immediate JNE relative
3
2
B8h-BFh
CJNE @Ri, #d, rel
Compare ind, immediate JNE relative
3
2
B6h,B7h
DJNZ Rn, rel
Decrement register, JNZ relative
2
2
D8h-DFh
DJNZ direct, rel
Decrement direct byte, JNZ relative
3
2
D5h
Miscellaneous Instruction
NOP
No operation
1
1
00h,A5h
Rn:
Any of the register R0 to R7
@Ri:
Indirect addressing using Register R0 or R1
#data:
immediate Data provided with Instruction
#data16: Immediate data included with instruction
bit:
address at the bit level
rel:
relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d:
Immediate Data supplied with instruction
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