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MAX1391ETB Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX1391ETB Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 18 page ference between the sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. The required acquisition time lengthens as the input signal’s source impedance increases. The acquisition time, tACQ, is the minimum time needed for the signal to be acquired. It is calculated by the following equation: tACQ ≥ 5.6 x (RSOURCE + RIN) x CIN + tPU where RSOURCE is the source impedance of the input signal. RIN = 500 Ω, which is the equivalent differential analog input resistance. CIN = 16pF, which is the equivalent differential analog input capacitance. tPU = 400ns. Note: tACQ is never less than 600ns and any source impedance below 400 Ω does not significantly affect the ADC’s AC performance. Analog Input Bandwidth The ADC’s input-tracking circuitry has a 4MHz full- power bandwidth, making it possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. Analog Input Range and Protection The MAX1391/MAX1394 produce a digital output that corresponds to the analog input voltage as long as the analog inputs are within their specified range. When operating the MAX1391 in unipolar mode (UNI/BIP = 1), the specified differential analog input range is from 0 to VREF. When operating in bipolar mode (UNI/BIP = 0), the differential analog input range is from -VREF/2 to +VREF/2 with a common-mode range of 0 to VDD. The MAX1394 has an input range from 0 to VREF. Internal protection diodes confine the analog input volt- age within the region of the analog power input rails (VDD, GND) and allow the analog input voltage to swing from GND - 0.3V to VDD + 0.3V without damage. Input voltages beyond GND - 0.3V and VDD + 0.3V forward bias the internal protection diodes. In this situation, limit the forward diode current to less than 50mA to avoid damage to the MAX1391/MAX1394. Output Data Format Figures 8, 9, and 10 illustrate the conversion timing for the MAX1391/MAX1394. Twelve SCLK cycles are required to read the conversion result and data on DOUT transitions on the falling edge of SCLK. The con- version result contains 4 zeros, followed by 8 data bits with the data in MSB-first format. For the MAX1391, data is straight binary for unipolar mode and two’s comple- ment for bipolar mode. For the MAX1394, data is always straight binary. Transfer Function Figure 5 shows the unipolar transfer function for the MAX1391/MAX1394. Figure 6 shows the bipolar trans- fer function for the MAX1391. Code transitions occur halfway between successive-integer LSB values. _______________________________________________________________________________________ 9 1.5V to 3.6V, 416ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 8-Bit, SAR ADCs + - HOLD TRACK CIN+ REF GND DAC CIN- RIN+ RIN- VDD/2 RSOURCE COMPARATOR HOLD HOLD AIN2 AIN1 (AIN+)* GND (AIN-)* ANALOG SIGNAL SOURCE MAX1391 MAX1394 (*INDICATES THE MAX1391) Figure 4. Equivalent Input Circuit |
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